diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Os/gtOs/mvXor.h b/tools/marvell/bin_hdr/inc/common/gtOs/mvXor.h
similarity index 100%
rename from tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Os/gtOs/mvXor.h
rename to tools/marvell/bin_hdr/inc/common/gtOs/mvXor.h
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Os/gtOs/mvXorRegs.h b/tools/marvell/bin_hdr/inc/common/gtOs/mvXorRegs.h
similarity index 100%
rename from tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Os/gtOs/mvXorRegs.h
rename to tools/marvell/bin_hdr/inc/common/gtOs/mvXorRegs.h
diff --git a/tools/marvell/bin_hdr/platform/Makefile b/tools/marvell/bin_hdr/platform/Makefile
index 250e385..c196bef 100755
--- a/tools/marvell/bin_hdr/platform/Makefile
+++ b/tools/marvell/bin_hdr/platform/Makefile
@@ -80,7 +80,7 @@
 CSRC_DRV = $(DRV)/mv_uart.c $(DRV)/mv_twsi.c $(DRV)/mv_time.c
 CSRC_UTILS = $(UTILS)/utils.c $(UTILS)/printf.c $(UTILS)/mvHwsSiliconIf.c
 CSRC_SYS_ENV = $(SYS_ENV)/mvSysEnvLib.c
-CSRC_BIN_HDR_DEBUG = $(BIN_HDR_DEBUG)/debug.c $(BIN_HDR_DEBUG)/lib_utils.c $(BIN_HDR_DEBUG)/command.c $(BIN_HDR_DEBUG)/mem.c
+CSRC_BIN_HDR_DEBUG = $(BIN_HDR_DEBUG)/debug.c $(BIN_HDR_DEBUG)/lib_utils.c $(BIN_HDR_DEBUG)/command.c $(BIN_HDR_DEBUG)/mem.c $(BIN_HDR_DEBUG)/xor_memtest.c
 
 ifeq "$(CONFIG_ALLEYCAT3)"  "y"
   CSRC_UTILS += $(UTILS)/mv_seq_exec_ext.c
diff --git a/tools/marvell/bin_hdr/platform/utils/debug/command.c b/tools/marvell/bin_hdr/platform/utils/debug/command.c
index a253aaf..bf13f4a 100644
--- a/tools/marvell/bin_hdr/platform/utils/debug/command.c
+++ b/tools/marvell/bin_hdr/platform/utils/debug/command.c
@@ -77,6 +77,7 @@
 int ir_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 int training_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_xorMemTest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 
 /* Commands Table
  * Every new command is added here, Thus it must be declared in
@@ -94,7 +95,9 @@
 	{ "cp", 4, do_mem_cp, "memory copy", "[.b, .w, .l] source target count"},
 	{ "ir", 2, ir_cmd, "ir	- reading and changing MV internal register values.\n", "address"},
 	{ "training", 1, training_cmd, "training	- prints the results of the DDR3 Training.\n"},
-	{ "mtest", 5, do_mem_mtest, "simple RAM read/write test", "[start [end [pattern [iterations]]]]"}
+	{ "mtest", 5, do_mem_mtest, "simple RAM read/write test", "[start [end [pattern [iterations]]]]"},
+	{ "xormtest", 4, do_xorMemTest, "run memory test based on XOR engine",
+		"[source [destination [size(bytes) [iterations]]]]"}
 };
 
 /* local functions definitions */
diff --git a/tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.c b/tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.c
new file mode 100644
index 0000000..43289c6
--- /dev/null
+++ b/tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.c
@@ -0,0 +1,314 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms.  Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED.  The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    *   Redistributions of source code must retain the above copyright notice,
+	    this list of conditions and the following disclaimer.
+
+    *   Redistributions in binary form must reproduce the above copyright
+		notice, this list of conditions and the following disclaimer in the
+		documentation and/or other materials provided with the distribution.
+
+    *   Neither the name of Marvell nor the names of its contributors may be
+		used to endorse or promote products derived from this software without
+		specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "command.h"
+#include "printf.h"
+#include "mvUart.h"
+#include "lib_utils.h"
+#include "mv_os.h"
+#include "soc_spec.h"
+#include "ddr3_hws_hw_training_def.h"
+#include "stdint.h"
+#include "gtOs/mvXor.h"
+#include "gtOs/mvXorRegs.h"
+#include "stdlib.h"
+#include "util.h"
+#include "xor_memtest.h"
+
+extern GT_U32 mvHwsDdr3TipMaxCSGet(GT_U32 devNum);
+
+/*******************************************************************************
+* fillKillerPattern
+*
+* DESCRIPTION:
+* Writes the killer pattern in the specified source address in DRAM
+*
+* INPUT:
+*	nBase		- base address to start writing to
+*	nSize		- size of the block in bytes
+*	nbusWidth	- bus width, must be multiply of 32
+*
+*******************************************************************************/
+void fillKillerPattern(MV_U32 nBase, MV_U32 nSize, MV_U32 nbusWidth)
+{
+	MV_U8 killerPatternBusState[ST_KP_LEN] = KILLER_PATTERN_BUS_STATE;
+	MV_U8 killerPatternBitState[ST_KP_LEN] = KILLER_PATTERN_BIT_STATE;
+	MV_U32 nOffset = 0;
+	MV_U32 nNumOfWord = nbusWidth / 32;
+	MV_U32 nPattern;
+	MV_U32 nIndex   = 0;
+	MV_U32 nVicBit  = BIT0;
+	MV_U32 nVicWord = 0;
+	MV_U32 nWord;
+
+	while (nOffset < nSize) {
+		if (nIndex == ST_KP_LEN) {
+			nIndex = 0;
+			nVicBit <<= 1;
+			if (nVicBit == 0) {
+				nVicBit = BIT0;
+				nVicWord++;
+				if (nVicWord == nNumOfWord)
+					nVicWord = 0;
+			}
+		}
+		for (nWord = 0; ((nWord < nNumOfWord) && (nOffset < nSize)); nWord++, nOffset += 0x4) {
+			nPattern = BUS_STATUS(killerPatternBusState[nIndex]);
+			if (nWord == nVicWord)
+				nPattern = ((killerPatternBitState[nIndex]) ?
+						(nPattern | nVicBit) : (nPattern & ~nVicBit));
+
+			MV_MEMIO_LE32_WRITE(nBase + nOffset, nPattern);
+		}
+		nIndex++;
+	}
+}
+
+/*******************************************************************************
+* configureMemoryMapping
+*
+* DESCRIPTION:
+* Opens memory windows in the XOR Engine to the DRAM and SRAM
+*
+*******************************************************************************/
+void configureMemoryMapping()
+{
+	MV_U32 max_cs;
+	MV_U32 uiCsEna = 0, cs_c;
+#ifndef MV88F672X
+	max_cs = mvHwsDdr3TipMaxCSGet(0);
+#else
+	max_cs = 2;
+#endif
+	for (cs_c = 0; cs_c < max_cs; cs_c++)
+		uiCsEna |= 1 << cs_c;
+
+	/* enable SRAM window */
+	uiCsEna |= 1 << SRAM_WIN_ID;
+	max_cs++;
+	/* configure XOR engine windows */
+	mvSysXorInit(max_cs, uiCsEna, 0x80000000, 0);
+
+	/* shrink first DRAM(CS0) window to 0x40000000 (bytes)
+	 * to avoid memory mapping conflict:
+	 * First DRAM(CS0) window starts in 0x0 and ends in 0x80000000
+	 * SRAM window starts in 0x40000000
+	 * Hence, there is a conflict */
+	MV_REG_WRITE(XOR_SIZE_MASK_REG(0, 0), 0x3FFF0000);
+}
+
+/*******************************************************************************
+* XORCalculateCRC
+*
+* DESCRIPTION:
+* Calculates crc32c using the XOR engine
+*
+* INPUT:
+*	nChannel	- channel number (0..3)
+*	nSrcAddr	- source address
+*	nByteCnt	- size of the block in bytes
+*
+* OUTPUT:
+*	res		- crc32c result
+*
+* RETURN:
+*	MV_ERROR, in case of any error in calculation
+*	MV_OK, otherwise
+*
+*******************************************************************************/
+MV_STATUS XORCalculateCRC(MV_U32 nChannel, MV_U32 nSrcAddr, MV_U32 nByteCnt, MV_U32 *res)
+{
+
+	MV_U32 nTimeout = XOR_ENGINE_TIMEOUT;
+	MV_XOR_DESC XorDesc;
+	MV_XOR_DESC *pXorDesc = &XorDesc;
+	MV_U32 nXorChannel = XOR_CHAN(nChannel);
+
+	/* align pointer address to be multiple of 32 */
+	pXorDesc = (MV_XOR_DESC *)(((MV_U32)((void *)pXorDesc + 32)) & ~(32 - 1));
+
+	memset((void *)pXorDesc, 0, sizeof(MV_CRC_DMA_DESC));
+
+	/* clean previous indication from engine */
+	MV_REG_WRITE(XOR_CAUSE_REG(XOR_UNIT(nChannel)), 0);
+
+	memset((void *)pXorDesc, 0, sizeof(MV_CRC_DMA_DESC));
+	pXorDesc->srcAdd0		= nSrcAddr;
+	pXorDesc->byteCnt		= nByteCnt;
+	pXorDesc->descCommand		= BIT30;
+	pXorDesc->phyNextDescPtr	= 0;
+	pXorDesc->status		= BIT31;
+	pXorDesc->crc32Result		= 0;
+
+	/* wait for previous transfer to finnish */
+	while (mvXorStateGet(nChannel) != MV_IDLE)
+		;
+
+	/* disable address override */
+	MV_REG_WRITE(XOR_OVERRIDE_CTRL_REG(nChannel), 0x0);
+
+	if (mvXorTransfer(nChannel, MV_CRC32, (MV_U32)pXorDesc) != MV_OK) {
+		mvPrintf("%s: Error during XOR CRC...!\n", __func__);
+		return MV_ERROR;
+	}
+
+	/* wait for the engine to finish */
+	while ((MV_REG_READ(XOR_CAUSE_REG(XOR_UNIT(nChannel))) & ((BIT1|BIT0) << (16*nXorChannel))) == 0) {
+		if (nTimeout-- == 0) {
+			mvPrintf("%s: XOR CRC timeout!!\n", __func__);
+			return MV_ERROR;
+		}
+	}
+
+	nTimeout = XOR_ENGINE_TIMEOUT;
+	while (mvXorStateGet(nChannel) != MV_IDLE) {
+		if (nTimeout-- == 0) {
+			mvPrintf("%s: XOR CRC timeout 0!!\n", __func__);
+			return MV_ERROR;
+		}
+	}
+
+	*res = pXorDesc->crc32Result;
+	return MV_OK;
+}
+
+/*******************************************************************************
+* do_xorMemTest
+*
+* DESCRIPTION:
+* The command run memory test that is based on the XOR engine
+*
+*******************************************************************************/
+int do_xorMemTest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	MV_STATUS status;
+	MV_U32 nBlockCRC, nOffsetInDest, nOffset, nCRC, i, nSourceAddr, nDestAddr;
+	MV_U32 sourceBase = SOURCE_ADDRESS_BASE;
+	MV_U32 destBase = DESTANTION_ADDRESS_BASE;
+	MV_U32 destSize = DESTANTION_SIZE;
+	MV_U32 iterations = 1;
+
+	if (argc > 1)
+		nSourceAddr = simple_strtoul(argv[1], NULL, 16);
+
+	if (argc > 2)
+		nDestAddr = simple_strtoul(argv[2], NULL, 16);
+
+	if (argc > 3)
+		destSize = simple_strtoul(argv[3], NULL, 16);
+
+	if (argc > 4)
+		iterations = simple_strtoul(argv[4], NULL, 16);
+
+	/* check destSize, must be multiply of 1MB */
+	if (destSize & (_1M - 1)) {
+		mvPrintf("Error: Destination size must be multiply of 0x%X(1MB)\n", _1M);
+		mvSysXorFinish();
+		return -1;
+	}
+
+	configureMemoryMapping();
+
+	/* write the killer pattern in the source block */
+	fillKillerPattern(sourceBase, BLOCK_SIZE, 64);
+	fillKillerPattern(sourceBase + BLOCK_SIZE, BLOCK_SIZE, 128);
+
+	status = XORCalculateCRC(2, sourceBase, TOTAL_BLOCK_SIZE, &nBlockCRC);
+	CHECK_CRC_STATUS(status);
+	mvPrintf("nBlockCRC %x\n", nBlockCRC);
+
+	/* Start copying blocks */
+	for (i = 0; i < iterations; i++) {
+		for (nOffsetInDest = 0; nOffsetInDest < destSize; nOffsetInDest += TOTAL_BLOCK_SIZE) {
+
+			/* Copy block to the current destination address*/
+			for (nOffset = 0; nOffset < TOTAL_BLOCK_SIZE; nOffset += CPU_BURST_SIZE) {
+				nSourceAddr = sourceBase + nOffset;
+				nDestAddr = destBase + nOffsetInDest + nOffset;
+				MV_PLD_RANGE(nDestAddr, nDestAddr + CPU_BURST_SIZE);
+				memcpy((void *)nDestAddr, (void *)nSourceAddr, CPU_BURST_SIZE);
+				MV_FLUSH_CACHE_L1(nDestAddr, nDestAddr + CPU_BURST_SIZE);
+			}
+		}
+
+		/* Check the copied blocks in destination */
+		for (nOffsetInDest = 0; nOffsetInDest < destSize; nOffsetInDest += TOTAL_BLOCK_SIZE) {
+			nDestAddr = destBase + nOffsetInDest;
+			status = XORCalculateCRC(2, nDestAddr, TOTAL_BLOCK_SIZE, &nCRC);
+			CHECK_CRC_STATUS(status);
+			if (nCRC != nBlockCRC) {
+				mvPrintf("Error at Block start address %X\n", nDestAddr);
+				mvPrintf("CRC was %X expected %X\n", nCRC, nBlockCRC);
+				mvSysXorFinish();
+				return -1;
+			}
+		}
+		mvPrintf("\b\b\b\b%4d", i);
+	}
+	mvPrintf("\b\b\b\b");
+	mvPrintf("MemTest end successfully\n");
+	mvSysXorFinish();
+
+	return 0;
+}
diff --git a/tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.h b/tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.h
new file mode 100644
index 0000000..91d7ab7
--- /dev/null
+++ b/tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.h
@@ -0,0 +1,145 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms.  Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED.  The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    *   Redistributions of source code must retain the above copyright notice,
+	    this list of conditions and the following disclaimer.
+
+    *   Redistributions in binary form must reproduce the above copyright
+		notice, this list of conditions and the following disclaimer in the
+		documentation and/or other materials provided with the distribution.
+
+    *   Neither the name of Marvell nor the names of its contributors may be
+		used to endorse or promote products derived from this software without
+		specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define SRAM_WIN_ID		0x4
+#define SRAM_WIN_BASE		0x40000000
+
+#define XOR_ENGINE_TIMEOUT	0x5000000
+
+#define ST_KP_LEN		59
+#define ONE			0xffffffff
+#define ZERO			0
+#define BUS_STATUS(nValue)	((nValue) ? ONE : ZERO)
+#define BIT(X)			(0x1 << X)
+
+#define NUM_OF_DESC		8
+#define DESC_SIZE		_8M
+
+#define SOURCE_ADDRESS_BASE    0x83000000
+#define BLOCK_SIZE             _1M
+#define TOTAL_BLOCK_SIZE       (BLOCK_SIZE*2)
+#define KILLER_64BIT_BASE      SOURCE_ADDRESS_BASE
+#define KILLER_128BIT_BASE     (KILLER_64BIT_BASE + BLOCK_SIZE)
+#define CPU_BURST_SIZE         _1K
+
+#define DESTANTION_ADDRESS_BASE 0x84000000
+#define DESTANTION_SIZE         _128M
+
+#define NUM_OF_XOR_ENGINE              4
+#define XOR_BLOCK_SIZE                 (_16M - 1)
+#define XOR_SOURCE_ADDRESS(nXorNum)    (0x10000000 + _128M*nXorNum)
+#define XOR_DEST_ADDRESS(nXorNum)      (XOR_SOURCE_ADDRESS(nXorNum) + (DESC_SIZE*NUM_OF_DESC))
+
+#define MV_PLD(Address)\
+{\
+	__asm__ __volatile__("pld [%0]" : : "r" (Address));\
+}
+
+#define MV_PLD_RANGE(from, to)\
+{\
+	MV_U32 addr;\
+	for (addr = from; addr < to; addr += 32) {\
+		MV_PLD(addr);\
+	} \
+}
+
+#define CHECK_CRC_STATUS(status)\
+{\
+	if (status != MV_OK) {\
+		mvPrintf("Failed to calculate CRC32\n");\
+		return 1;\
+	} \
+}
+
+void cache_inv(MV_U32 dest);
+void flush_l1_v7(MV_U32 dest);
+
+#define MV_FLUSH_CACHE_L1(from, to)\
+{\
+	MV_U32 addr;\
+	for (addr = from; addr < to; addr += 32) {\
+		cache_inv(addr);\
+		flush_l1_v7(addr);\
+	} \
+}
+
+#define KILLER_PATTERN_BUS_STATE\
+	{\
+		0, 0, 0, 1, 1, 1, 0, 1, 0, 1,\
+		0, 0, 1, 0, 1, 0, 1, 0, 1, 0,\
+		1, 0, 1, 0, 0, 1, 0, 1, 0, 0,\
+		0, 1, 1, 1, 0, 0, 1, 1, 0, 1,\
+		0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\
+		1, 1, 0, 1, 1, 0, 0\
+	}
+
+#define KILLER_PATTERN_BIT_STATE\
+	{\
+		1, 0, 1, 1, 0, 0, 1, 0, 1, 0,\
+		1, 1, 0, 1, 0, 0, 1, 0, 1, 0,\
+		1, 0, 1, 1, 0, 1, 0, 1, 0, 0,\
+		0, 0, 0, 1, 0, 0, 1, 1, 0, 1,\
+		0, 1, 1, 0, 0, 1, 0, 1, 0, 0,\
+		0, 0, 0, 1, 1, 1, 1\
+	}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
index bae76b2..f02ae98 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
@@ -71,34 +71,53 @@
 #endif
 
 static GT_U32 uiXorRegsCtrlBackup;
-static GT_U32 uiXorRegsBaseBackup[MAX_CS];
-static GT_U32 uiXorRegsMaskBackup[MAX_CS];
+static GT_U32 uiXorRegsBaseBackup[MAX_CS + 1];
+static GT_U32 uiXorRegsMaskBackup[MAX_CS + 1];
 
 extern GT_U32 mvHwsDdr3TipMaxCSGet(GT_U32 devNum);
 
+/*******************************************************************************
+* mvSysXorInit
+*
+* DESCRIPTION:
+*               This function initialize the XOR unit's windows.
+* INPUT:
+*       uiNumOfCS	- number of enabled chip select
+*	uiCsEna		- bitmap of enabled chip selects:
+*				bit[i] = 1 if chip select i is enabled (for 1 <= i <= 3)
+*				bit[4] = if SRAM window is enabled
+*	csSize		- size of DRAM chip select
+*	baseDelta	- base start of the DRAM windows
+*
+*
+*******************************************************************************/
 GT_VOID mvSysXorInit(GT_U32 uiNumOfCS, GT_U32 uiCsEna, GT_U32 csSize, GT_U32 baseDelta)
 {
-	GT_U32 uiReg,ui,uiBase,uiCsCount;
+	GT_U32 uiReg, ui, uiBase, uiCsCount, sizeMask;
 
 	uiXorRegsCtrlBackup = MV_REG_READ(XOR_WINDOW_CTRL_REG(0, 0));
-	for(ui=0;ui<MAX_CS;ui++)
+	for(ui = 0; ui < MAX_CS + 1; ui++)
 		uiXorRegsBaseBackup[ui] = MV_REG_READ(XOR_BASE_ADDR_REG(0, ui));
-	for(ui=0;ui<MAX_CS;ui++)
+	for(ui = 0; ui < MAX_CS + 1; ui++)
 		uiXorRegsMaskBackup[ui] = MV_REG_READ(XOR_SIZE_MASK_REG(0, ui));
 
 	uiReg = 0;
-	for(ui=0;ui<(uiNumOfCS);ui++) {
-		uiReg |= (0x1 << (ui)); 					/* 	Enable Window x for each CS */
-		uiReg |= (0x3 << ((ui*2)+16)); 				/* 	Enable Window x for each CS */
+	for (uiCsCount = 0, ui = 0; uiCsCount < uiNumOfCS && ui < 8; ui++) {
+		if(uiCsEna & (1 << ui)) {
+			uiReg |= (0x1 << (ui));			/* Enable Window x for each CS */
+			uiReg |= (0x3 << ((ui*2)+16)); 		/* Enable Window x for each CS */
+			uiCsCount++;
+		}
 	}
 
 	MV_REG_WRITE(XOR_WINDOW_CTRL_REG(0, 0), uiReg);
 
-	uiCsCount = 0;
-	for(ui=0;ui<uiNumOfCS;ui++) {
+	for (uiCsCount = 0, ui = 0; uiCsCount < uiNumOfCS && ui < 8; ui++) {
 		if(uiCsEna & (1<<ui)) {
 			/* window x - Base - 0x00000000, Attribute 0x0E - DRAM */
 			uiBase = csSize*ui + baseDelta;
+			/* fixed size 2GB for each CS */
+			sizeMask = 0x7FFF0000;
 			switch(ui) {
 				case 0:
 					uiBase |= 0xE00;
@@ -112,12 +131,16 @@
 				case 3:
 					uiBase |= 0x700;
 					break;
+				case 4: /* SRAM */
+					uiBase = 0x40000000;
+					uiBase |= 0x1F00; /* configure as shared transaction */
+					sizeMask = 0xF0000;
 			}
 
-			MV_REG_WRITE(XOR_BASE_ADDR_REG(0, uiCsCount), uiBase);
+			MV_REG_WRITE(XOR_BASE_ADDR_REG(0, ui), uiBase);
 
 			/* window x - Size*/
-			MV_REG_WRITE(XOR_SIZE_MASK_REG(0, uiCsCount), 0x7FFF0000);
+			MV_REG_WRITE(XOR_SIZE_MASK_REG(0, ui), sizeMask);
 			uiCsCount++;
 		}
 	}
@@ -131,9 +154,9 @@
 	GT_U32 ui;
 
 	MV_REG_WRITE(XOR_WINDOW_CTRL_REG(0, 0), uiXorRegsCtrlBackup);
-	for(ui=0;ui<MAX_CS;ui++)
+	for(ui = 0; ui < MAX_CS + 1; ui++)
 		MV_REG_WRITE(XOR_BASE_ADDR_REG(0, ui), uiXorRegsBaseBackup[ui]);
-	for(ui=0;ui<MAX_CS;ui++)
+	for(ui = 0; ui < MAX_CS + 1; ui++)
 		MV_REG_WRITE(XOR_SIZE_MASK_REG(0, ui), uiXorRegsMaskBackup[ui]);
 
 	MV_REG_WRITE(XOR_ADDR_OVRD_REG(0, 0), 0);
@@ -414,4 +437,103 @@
     mvPrintf("DDR Training Sequence - End scrubbing \n");
 }
 
+/*******************************************************************************
+* mvXorTransfer - Transfer data from source to destination on one of
+*                 three modes (XOR,CRC32,DMA)
+*
+* DESCRIPTION:
+*       This function initiates XOR channel, according to function parameters,
+*       in order to perform XOR or CRC32 or DMA transaction.
+*       To gain maximum performance the user is asked to keep the following
+*       restrictions:
+*       1) Selected engine is available (not busy).
+*       1) This module does not take into consideration CPU MMU issues.
+*          In order for the XOR engine to access the appropreate source
+*          and destination, address parameters must be given in system
+*          physical mode.
+*       2) This API does not take care of cache coherency issues. The source,
+*          destination and in case of chain the descriptor list are assumed
+*          to be cache coherent.
+*       4) Parameters validity. For example, does size parameter exceeds
+*          maximum byte count of descriptor mode (16M or 64K).
+*
+* INPUT:
+*       chan          - XOR channel number. See GT_XOR_CHANNEL enumerator.
+*       xorType       - One of three: XOR, CRC32 and DMA operations.
+*       xorChainPtr   - address of chain pointer
+*
+* OUTPUT:
+*       None.
+*
+* RETURS:
+*       GT_BAD_PARAM if parameters to function invalid, GT_OK otherwise.
+*
+*******************************************************************************/
+GT_STATUS mvXorTransfer(GT_U32 chan, MV_XOR_TYPE xorType, GT_U32 xorChainPtr)
+{
+	GT_U32 temp;
 
+	/* Parameter checking */
+	if (chan >= MV_XOR_MAX_CHAN) {
+		DB(mvPrintf("%s: ERR. Invalid chan num %d\n", __func__, chan));
+		return GT_BAD_PARAM;
+	}
+	if (MV_ACTIVE == mvXorStateGet(chan)) {
+		DB(mvPrintf("%s: ERR. Channel is already active\n", __func__));
+		return GT_BUSY;
+	}
+	if (0x0 == xorChainPtr) {
+		DB(mvPrintf("%s: ERR. xorChainPtr is NULL pointer\n", __func__));
+		return GT_BAD_PARAM;
+	}
+
+	/* read configuration register and mask the operation mode field */
+	temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
+	temp &= ~XEXCR_OPERATION_MODE_MASK;
+
+	switch (xorType) {
+	case MV_XOR:
+		if (0 != (xorChainPtr & XEXDPR_DST_PTR_XOR_MASK)) {
+			DB(mvPrintf("%s: ERR. Invalid chain pointer (bits [5:0] must "
+				      "be cleared)\n", __func__));
+			return GT_BAD_PARAM;
+		}
+		/* set the operation mode to XOR */
+		temp |= XEXCR_OPERATION_MODE_XOR;
+		break;
+
+	case MV_DMA:
+		if (0 != (xorChainPtr & XEXDPR_DST_PTR_DMA_MASK)) {
+			DB(mvPrintf("%s: ERR. Invalid chain pointer (bits [4:0] must "
+				      "be cleared)\n", __func__));
+			return GT_BAD_PARAM;
+		}
+		/* set the operation mode to DMA */
+		temp |= XEXCR_OPERATION_MODE_DMA;
+		break;
+
+	case MV_CRC32:
+		if (0 != (xorChainPtr & XEXDPR_DST_PTR_CRC_MASK)) {
+			DB(mvPrintf("%s: ERR. Invalid chain pointer (bits [4:0] must "
+				      "be cleared)\n", __func__));
+			return GT_BAD_PARAM;
+		}
+		/* set the operation mode to CRC32 */
+		temp |= XEXCR_OPERATION_MODE_CRC;
+		break;
+
+	default:
+		return GT_BAD_PARAM;
+	}
+
+	/* write the operation mode to the register */
+	MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp);
+	/* update the NextDescPtr field in the XOR Engine [0..1] Next Descriptor
+	   Pointer Register (XExNDPR) */
+	MV_REG_WRITE(XOR_NEXT_DESC_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xorChainPtr);
+
+	/* start transfer */
+	MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), XEXACTR_XESTART_MASK);
+
+	return GT_OK;
+}