/****************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on               Mon May  4 10:42:12 2015
 *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
 *                     (minus title and desc)
 *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
 *
 * Compiled with:  RDB Utility                combo_header.pl
 *                 RDB.pm                     15517
 *                 unknown                    unknown
 *                 Perl Interpreter           5.008005
 *                 Operating System           linux
 *
 *
 ***************************************************************************/

#ifndef BCHP_SWITCH_REG_H__
#define BCHP_SWITCH_REG_H__

/***************************************************************************
 *SWITCH_REG
 ***************************************************************************/
#define BCHP_SWITCH_REG_SWITCH_CNTRL             0x04e40000 /* [RW] Switch Control Register */
#define BCHP_SWITCH_REG_SWITCH_STATUS            0x04e40004 /* [RO] Switch Status Register */
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG       0x04e40008 /* [RW] Direct Data Write Register */
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG        0x04e4000c /* [RO] Direct Data Read Register */
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT 0x04e40010 /* [RW] LED Serial Refresh Time Unit Register */
#define BCHP_SWITCH_REG_SWITCH_REVISION          0x04e40018 /* [RO] SWITCH Revision Control Register */
#define BCHP_SWITCH_REG_PHY_REVISION             0x04e4001c /* [RO] PHY Revision Control Register */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL           0x04e40020 /* [RW] PHY Test Control Register */
#define BCHP_SWITCH_REG_QPHY_CNTRL               0x04e40024 /* [RW] Quad GPHY Control Register */
#define BCHP_SWITCH_REG_QPHY_STATUS              0x04e40028 /* [RO] Quad GPHY Status Register */
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL     0x04e40088 /* [RW] LED port Blink Rate Control Register */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL         0x04e4008c /* [RW] LED Serial Control Register */
#define BCHP_SWITCH_REG_LED_0_CNTRL              0x04e40090 /* [RW] LED port 0 Control Register */
#define BCHP_SWITCH_REG_LED_1_CNTRL              0x04e40094 /* [RW] LED port 1 Control Register */
#define BCHP_SWITCH_REG_LED_2_CNTRL              0x04e40098 /* [RW] LED port 2 Control Register */
#define BCHP_SWITCH_REG_LED_3_CNTRL              0x04e4009c /* [RW] LED port 3 Control Register */
#define BCHP_SWITCH_REG_LED_4_CNTRL              0x04e400a0 /* [RW] LED port 4 Control Register */
#define BCHP_SWITCH_REG_LED_5_CNTRL              0x04e400a4 /* [RW] LED port 5 Control Register */
#define BCHP_SWITCH_REG_LED_7_CNTRL              0x04e400a8 /* [RW] LED port 7 Control Register */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL            0x04e400b0 /* [RW] RGMII port 9 Control Register */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS        0x04e400b4 /* [RW] RGMII port 9 InBand Status Register */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL 0x04e400b8 /* [RW] RGMII port 9 RX Clock Delay Control Register */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL           0x04e400bc /* [RW] RGMII port 10 Control Register */
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS       0x04e400c0 /* [RW] RGMII port 10 InBand Status Register */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL 0x04e400c4 /* [RW] RGMII port 10 RX Clock Delay Control Register */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL     0x04e40150 /* [RW] RGMII port 9 ATE RX Control Register */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS    0x04e40154 /* [RO] RGMII port 9 ATE RX Status Register */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0   0x04e40158 /* [RW] RGMII port 9 ATE TX Control 0 Register */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1   0x04e4015c /* [RW] RGMII port 9 ATE TX Control 1 Register */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL    0x04e40160 /* [RW] RGMII port 10 ATE RX Control Register */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS   0x04e40164 /* [RO] RGMII port 10 ATE RX Status Register */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0  0x04e40168 /* [RW] RGMII port 10 ATE TX Control 0 Register */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1  0x04e4016c /* [RW] RGMII port 10 ATE TX Control 1 Register */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL      0x04e401a8 /* [RW] Aggregate LED Control Register */
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL 0x04e401ac /* [RW] Aggregate LED Blink Rate Control Register */
#define BCHP_SWITCH_REG_SPARE_CNTRL              0x04e401b0 /* [RW] Spare Control Register */
#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL    0x04e401b4 /* [RW] Switch PHY Interrupt Control Register */

/***************************************************************************
 *SWITCH_CNTRL - Switch Control Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_CNTRL :: reserved0 [31:15] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_MASK                0xffff8000
#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_SHIFT               15

/* SWITCH_REG :: SWITCH_CNTRL :: p4_hs_sel [14:14] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p4_hs_sel_MASK                0x00004000
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p4_hs_sel_SHIFT               14
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p4_hs_sel_DEFAULT             0x00000000

/* SWITCH_REG :: SWITCH_CNTRL :: sw_pseudo_phy_addr [13:09] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_MASK       0x00003e00
#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_SHIFT      9
#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_DEFAULT    0x0000001d

/* SWITCH_REG :: SWITCH_CNTRL :: sw_mdio_en [08:08] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_MASK               0x00000100
#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_SHIFT              8
#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_CNTRL :: p5_2_5g_en [07:07] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_MASK               0x00000080
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_SHIFT              7
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_CNTRL :: p7_2_5g_en [06:06] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_MASK               0x00000040
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_SHIFT              6
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_CNTRL :: p8_2_5g_en [05:05] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_MASK               0x00000020
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_SHIFT              5
#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_CNTRL :: moca_bp_en [04:04] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_MASK               0x00000010
#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_SHIFT              4
#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_CNTRL :: pda_mux_sel [03:03] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_MASK              0x00000008
#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_SHIFT             3
#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_DEFAULT           0x00000001

/* SWITCH_REG :: SWITCH_CNTRL :: pda_chain_en [02:02] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_MASK             0x00000004
#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_SHIFT            2
#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_DEFAULT          0x00000001

/* SWITCH_REG :: SWITCH_CNTRL :: spi_dis [01:01] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_MASK                  0x00000002
#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_SHIFT                 1
#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_DEFAULT               0x00000001

/* SWITCH_REG :: SWITCH_CNTRL :: mdio_master_sel [00:00] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_MASK          0x00000001
#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_SHIFT         0
#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_DEFAULT       0x00000000

/***************************************************************************
 *SWITCH_STATUS - Switch Status Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_STATUS :: reserved0 [31:01] */
#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_MASK               0xfffffffe
#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_SHIFT              1

/* SWITCH_REG :: SWITCH_STATUS :: sw_init_done [00:00] */
#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_MASK            0x00000001
#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_SHIFT           0
#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_DEFAULT         0x00000000

/***************************************************************************
 *DIR_DATA_WRITE_REG - Direct Data Write Register
 ***************************************************************************/
/* SWITCH_REG :: DIR_DATA_WRITE_REG :: write_data [31:00] */
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_MASK         0xffffffff
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_SHIFT        0
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_DEFAULT      0x00000000

/***************************************************************************
 *DIR_DATA_READ_REG - Direct Data Read Register
 ***************************************************************************/
/* SWITCH_REG :: DIR_DATA_READ_REG :: read_data [31:00] */
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_MASK           0xffffffff
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_SHIFT          0
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_DEFAULT        0x00000000

/***************************************************************************
 *LED_SERIAL_REFRESH_TIME_UNIT - LED Serial Refresh Time Unit Register
 ***************************************************************************/
/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: reserved0 [31:24] */
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_MASK 0xff000000
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_SHIFT 24

/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: refresh_time_unit [23:00] */
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_MASK 0x00ffffff
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_SHIFT 0
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_DEFAULT 0x0001e847

/***************************************************************************
 *SWITCH_REVISION - SWITCH Revision Control Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_REVISION :: SF2_rev [31:16] */
#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_MASK               0xffff0000
#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_SHIFT              16
#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_REVISION :: switch_top_rev [15:00] */
#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_MASK        0x0000ffff
#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_SHIFT       0
#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_DEFAULT     0x00000000

/***************************************************************************
 *PHY_REVISION - PHY Revision Control Register
 ***************************************************************************/
/* SWITCH_REG :: PHY_REVISION :: quad_phy_rev [31:16] */
#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_MASK             0xffff0000
#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_SHIFT            16
#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_DEFAULT          0x00000000

/* SWITCH_REG :: PHY_REVISION :: single_phy_rev [15:00] */
#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_MASK           0x0000ffff
#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_SHIFT          0
#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_DEFAULT        0x00000000

/***************************************************************************
 *PHY_TEST_CNTRL - PHY Test Control Register
 ***************************************************************************/
/* SWITCH_REG :: PHY_TEST_CNTRL :: reserved0 [31:06] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_MASK              0xffffffc0
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_SHIFT             6

/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_sel [05:03] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_MASK                0x00000038
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_SHIFT               3
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_DEFAULT             0x00000000

/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_mode [02:01] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_MASK          0x00000006
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_SHIFT         1
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_DEFAULT       0x00000000

/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_en [00:00] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_MASK            0x00000001
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_SHIFT           0
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_DEFAULT         0x00000000

/***************************************************************************
 *QPHY_CNTRL - Quad GPHY Control Register
 ***************************************************************************/
/* SWITCH_REG :: QPHY_CNTRL :: reserved0 [31:17] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_MASK                  0xfffe0000
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_SHIFT                 17

/* SWITCH_REG :: QPHY_CNTRL :: phy_phyad [16:12] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_MASK                  0x0001f000
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_SHIFT                 12
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_DEFAULT               0x00000001

/* SWITCH_REG :: QPHY_CNTRL :: reserved1 [11:09] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_MASK                  0x00000e00
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_SHIFT                 9

/* SWITCH_REG :: QPHY_CNTRL :: phy_reset [08:08] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_MASK                  0x00000100
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_SHIFT                 8
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_DEFAULT               0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: ck25_dis [07:07] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_MASK                   0x00000080
#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_SHIFT                  7
#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_DEFAULT                0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: iddq_global_pwr [06:06] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_MASK            0x00000040
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_SHIFT           6
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_DEFAULT         0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: force_dll_en [05:05] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_MASK               0x00000020
#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_SHIFT              5
#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_DEFAULT            0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: ext_pwr_down [04:01] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_MASK               0x0000001e
#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_SHIFT              1
#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_DEFAULT            0x0000000f

/* SWITCH_REG :: QPHY_CNTRL :: iddq_bias [00:00] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_MASK                  0x00000001
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_SHIFT                 0
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_DEFAULT               0x00000001

/***************************************************************************
 *QPHY_STATUS - Quad GPHY Status Register
 ***************************************************************************/
/* SWITCH_REG :: QPHY_STATUS :: reserved0 [31:16] */
#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_MASK                 0xffff0000
#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_SHIFT                16

/* SWITCH_REG :: QPHY_STATUS :: mac_gphy_cfg_test_en [15:15] */
#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_MASK      0x00008000
#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_SHIFT     15
#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_DEFAULT   0x00000000

/* SWITCH_REG :: QPHY_STATUS :: mac_gphy_cfg_test_mode [14:13] */
#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_MASK    0x00006000
#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_SHIFT   13
#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_DEFAULT 0x00000000

/* SWITCH_REG :: QPHY_STATUS :: lock_recovery_clk [12:09] */
#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_MASK         0x00001e00
#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_SHIFT        9
#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_DEFAULT      0x00000000

/* SWITCH_REG :: QPHY_STATUS :: pll_lock [08:08] */
#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_MASK                  0x00000100
#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_SHIFT                 8
#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_DEFAULT               0x00000000

/* SWITCH_REG :: QPHY_STATUS :: energy_det_apd [07:04] */
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_MASK            0x000000f0
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_SHIFT           4
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_DEFAULT         0x00000000

/* SWITCH_REG :: QPHY_STATUS :: energy_det_masked [03:00] */
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_MASK         0x0000000f
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_SHIFT        0
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_DEFAULT      0x00000000

/***************************************************************************
 *LED_BLINK_RATE_CNTRL - LED port Blink Rate Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_MASK      0xffff0000
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT     16
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT   0x00000320

/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_MASK     0x0000ffff
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT    0
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT  0x00000320

/***************************************************************************
 *LED_SERIAL_CNTRL - LED Serial Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_SERIAL_CNTRL :: reserved0 [31:16] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_MASK            0xffff0000
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_SHIFT           16

/* SWITCH_REG :: LED_SERIAL_CNTRL :: port_en [15:08] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_MASK              0x0000ff00
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_SHIFT             8
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_DEFAULT           0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: smode [07:07] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_MASK                0x00000080
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_SHIFT               7
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_DEFAULT             0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_frequency [06:06] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_MASK   0x00000040
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_SHIFT  6
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_DEFAULT 0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_pol [05:05] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_MASK         0x00000020
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_SHIFT        5
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_DEFAULT      0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: refresh_period [04:00] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_MASK       0x0000001f
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_SHIFT      0
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_DEFAULT    0x00000004

/***************************************************************************
 *LED_0_CNTRL - LED port 0 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_0_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_0_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_0_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_0_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_0_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_0_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_1_CNTRL - LED port 1 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_1_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_1_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_1_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_1_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_1_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_1_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_2_CNTRL - LED port 2 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_2_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_2_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_2_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_2_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_2_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_2_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_3_CNTRL - LED port 3 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_3_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_3_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_3_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_3_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_3_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_3_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_4_CNTRL - LED port 4 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_4_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_4_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_4_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_4_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_4_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_4_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_4_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_4_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_5_CNTRL - LED port 5 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_5_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_5_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_5_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_5_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_5_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_5_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_5_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_5_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_7_CNTRL - LED port 7 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_7_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_7_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_7_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_7_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_7_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_7_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *RGMII_9_CNTRL - RGMII port 9 Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_CNTRL :: reserved0 [31:16] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_MASK               0xffff0000
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_SHIFT              16

/* SWITCH_REG :: RGMII_9_CNTRL :: col_crs_mask [15:15] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_col_crs_mask_MASK            0x00008000
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_col_crs_mask_SHIFT           15
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_col_crs_mask_DEFAULT         0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rx_err_mask [14:14] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_err_mask_MASK             0x00004000
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_err_mask_SHIFT            14
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_err_mask_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: lpi_count [13:09] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_MASK               0x00003e00
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_SHIFT              9
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_DEFAULT            0x0000000f

/* SWITCH_REG :: RGMII_9_CNTRL :: tx_clk_stop_en [08:08] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_MASK          0x00000100
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_SHIFT         8
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_DEFAULT       0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: tx_pause_en [07:07] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_MASK             0x00000080
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_SHIFT            7
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rx_pause_en [06:06] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_MASK             0x00000040
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_SHIFT            6
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rvmii_ref_sel [05:05] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_MASK           0x00000020
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_SHIFT          5
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_DEFAULT        0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: port_mode [04:02] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_MASK               0x0000001c
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_SHIFT              2
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_DEFAULT            0x00000003

/* SWITCH_REG :: RGMII_9_CNTRL :: id_mode_dis [01:01] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_MASK             0x00000002
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_SHIFT            1
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rgmii_mode_en [00:00] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_MASK           0x00000001
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_SHIFT          0
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_DEFAULT        0x00000000

/***************************************************************************
 *RGMII_9_IB_STATUS - RGMII port 9 InBand Status Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_IB_STATUS :: reserved0 [31:05] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_MASK           0xffffffe0
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_SHIFT          5

/* SWITCH_REG :: RGMII_9_IB_STATUS :: ib_status_ovrd [04:04] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_ib_status_ovrd_MASK      0x00000010
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_ib_status_ovrd_SHIFT     4
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_ib_status_ovrd_DEFAULT   0x00000000

/* SWITCH_REG :: RGMII_9_IB_STATUS :: link_decode [03:03] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_MASK         0x00000008
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_SHIFT        3
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_DEFAULT      0x00000000

/* SWITCH_REG :: RGMII_9_IB_STATUS :: duplex_decode [02:02] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_MASK       0x00000004
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_SHIFT      2
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_DEFAULT    0x00000000

/* SWITCH_REG :: RGMII_9_IB_STATUS :: speed_decode [01:00] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_MASK        0x00000003
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_SHIFT       0
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_DEFAULT     0x00000000

/***************************************************************************
 *RGMII_9_RX_CLOCK_DELAY_CNTRL - RGMII port 9 RX Clock Delay Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK  0x00000040
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_MASK   0x00000020
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT  5
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_MASK     0x00000010
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT    4
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT  0x00000000

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_MASK     0x0000000c
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_SHIFT    2
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT  0x00000002

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_MASK     0x00000003
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT    0
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT  0x00000000

/***************************************************************************
 *RGMII_10_CNTRL - RGMII port 10 Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_CNTRL :: reserved0 [31:16] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_reserved0_MASK              0xffff0000
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_reserved0_SHIFT             16

/* SWITCH_REG :: RGMII_10_CNTRL :: col_crs_mask [15:15] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_col_crs_mask_MASK           0x00008000
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_col_crs_mask_SHIFT          15
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_col_crs_mask_DEFAULT        0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: rx_err_mask [14:14] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_err_mask_MASK            0x00004000
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_err_mask_SHIFT           14
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_err_mask_DEFAULT         0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: lpi_count [13:09] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_MASK              0x00003e00
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_SHIFT             9
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_DEFAULT           0x0000000f

/* SWITCH_REG :: RGMII_10_CNTRL :: tx_clk_stop_en [08:08] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_MASK         0x00000100
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_SHIFT        8
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_DEFAULT      0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: tx_pause_en [07:07] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_MASK            0x00000080
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_SHIFT           7
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_DEFAULT         0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: rx_pause_en [06:06] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_MASK            0x00000040
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_SHIFT           6
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_DEFAULT         0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: rvmii_ref_sel [05:05] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_MASK          0x00000020
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_SHIFT         5
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_DEFAULT       0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: port_mode [04:02] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_MASK              0x0000001c
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_SHIFT             2
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_DEFAULT           0x00000003

/* SWITCH_REG :: RGMII_10_CNTRL :: id_mode_dis [01:01] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_MASK            0x00000002
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_SHIFT           1
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_DEFAULT         0x00000000

/* SWITCH_REG :: RGMII_10_CNTRL :: rgmii_mode_en [00:00] */
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_MASK          0x00000001
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_SHIFT         0
#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_DEFAULT       0x00000000

/***************************************************************************
 *RGMII_10_IB_STATUS - RGMII port 10 InBand Status Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_IB_STATUS :: reserved0 [31:05] */
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_reserved0_MASK          0xffffffe0
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_reserved0_SHIFT         5

/* SWITCH_REG :: RGMII_10_IB_STATUS :: ib_status_ovrd [04:04] */
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_ib_status_ovrd_MASK     0x00000010
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_ib_status_ovrd_SHIFT    4
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_ib_status_ovrd_DEFAULT  0x00000000

/* SWITCH_REG :: RGMII_10_IB_STATUS :: link_decode [03:03] */
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_MASK        0x00000008
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_SHIFT       3
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_DEFAULT     0x00000000

/* SWITCH_REG :: RGMII_10_IB_STATUS :: duplex_decode [02:02] */
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_MASK      0x00000004
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_SHIFT     2
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_DEFAULT   0x00000000

/* SWITCH_REG :: RGMII_10_IB_STATUS :: speed_decode [01:00] */
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_MASK       0x00000003
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_SHIFT      0
#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_DEFAULT    0x00000000

/***************************************************************************
 *RGMII_10_RX_CLOCK_DELAY_CNTRL - RGMII port 10 RX Clock Delay Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8

/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK 0x00000040
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_MASK  0x00000020
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT 5
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_MASK    0x00000010
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT   4
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT 0x00000000

/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_MASK    0x0000000c
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_SHIFT   2
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT 0x00000002

/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_MASK    0x00000003
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT   0
#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_9_ATE_RX_CNTRL - RGMII port 9 ATE RX Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: reserved0 [31:24] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_reserved0_MASK        0xff000000
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_reserved0_SHIFT       24

/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: ate_en [23:23] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_MASK           0x00800000
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_SHIFT          23
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_DEFAULT        0x00000000

/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: good_count [22:18] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_MASK       0x007c0000
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_SHIFT      18
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_DEFAULT    0x00000004

/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: expected_data_1 [17:09] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_MASK  0x0003fe00
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_SHIFT 9
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_DEFAULT 0x00000000

/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: expected_data_0 [08:00] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_MASK  0x000001ff
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_SHIFT 0
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_9_ATE_RX_STATUS - RGMII port 9 ATE RX Status Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: reserved0 [31:19] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_reserved0_MASK       0xfff80000
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_reserved0_SHIFT      19

/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: rx_ok [18:18] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_MASK           0x00040000
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_SHIFT          18
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_DEFAULT        0x00000000

/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: received_data_1 [17:09] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_MASK 0x0003fe00
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_SHIFT 9
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_DEFAULT 0x00000000

/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: received_data_0 [08:00] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_MASK 0x000001ff
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_SHIFT 0
#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_9_ATE_TX_CNTRL_0 - RGMII port 9 ATE TX Control 0 Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: reserved0 [31:02] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_reserved0_MASK      0xfffffffc
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_reserved0_SHIFT     2

/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: start_stop [01:01] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_MASK     0x00000002
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_SHIFT    1
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_DEFAULT  0x00000000

/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: start_stop_ovrd [00:00] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_MASK 0x00000001
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_SHIFT 0
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_9_ATE_TX_CNTRL_1 - RGMII port 9 ATE TX Control 1 Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: reserved0 [31:18] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_reserved0_MASK      0xfffc0000
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_reserved0_SHIFT     18

/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: tx_data_1 [17:09] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_MASK      0x0003fe00
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_SHIFT     9
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_DEFAULT   0x00000000

/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: tx_data_0 [08:00] */
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_MASK      0x000001ff
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_SHIFT     0
#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_DEFAULT   0x00000000

/***************************************************************************
 *RGMII_10_ATE_RX_CNTRL - RGMII port 10 ATE RX Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: reserved0 [31:24] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_reserved0_MASK       0xff000000
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_reserved0_SHIFT      24

/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: ate_en [23:23] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_MASK          0x00800000
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_SHIFT         23
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_DEFAULT       0x00000000

/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: good_count [22:18] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_MASK      0x007c0000
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_SHIFT     18
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_DEFAULT   0x00000004

/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: expected_data_1 [17:09] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_MASK 0x0003fe00
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_SHIFT 9
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_DEFAULT 0x00000000

/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: expected_data_0 [08:00] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_MASK 0x000001ff
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_SHIFT 0
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_10_ATE_RX_STATUS - RGMII port 10 ATE RX Status Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: reserved0 [31:19] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_reserved0_MASK      0xfff80000
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_reserved0_SHIFT     19

/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: rx_ok [18:18] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_MASK          0x00040000
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_SHIFT         18
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_DEFAULT       0x00000000

/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: received_data_1 [17:09] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_MASK 0x0003fe00
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_SHIFT 9
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_DEFAULT 0x00000000

/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: received_data_0 [08:00] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_MASK 0x000001ff
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_SHIFT 0
#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_10_ATE_TX_CNTRL_0 - RGMII port 10 ATE TX Control 0 Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: reserved0 [31:02] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_reserved0_MASK     0xfffffffc
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_reserved0_SHIFT    2

/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: start_stop [01:01] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_MASK    0x00000002
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_SHIFT   1
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_DEFAULT 0x00000000

/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: start_stop_ovrd [00:00] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_MASK 0x00000001
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_SHIFT 0
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_DEFAULT 0x00000000

/***************************************************************************
 *RGMII_10_ATE_TX_CNTRL_1 - RGMII port 10 ATE TX Control 1 Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: reserved0 [31:18] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_reserved0_MASK     0xfffc0000
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_reserved0_SHIFT    18

/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: tx_data_1 [17:09] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_MASK     0x0003fe00
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_SHIFT    9
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_DEFAULT  0x00000000

/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: tx_data_0 [08:00] */
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_MASK     0x000001ff
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_SHIFT    0
#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_DEFAULT  0x00000000

/***************************************************************************
 *AGGREGATE_LED_CNTRL - Aggregate LED Control Register
 ***************************************************************************/
/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: reserved0 [31:14] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_reserved0_MASK         0xffffc000
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_reserved0_SHIFT        14

/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: lnk_pol_sel [13:13] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_MASK       0x00002000
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_SHIFT      13
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_DEFAULT    0x00000000

/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: act_pol_sel [12:12] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_MASK       0x00001000
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_SHIFT      12
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_DEFAULT    0x00000000

/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: act_sel [11:11] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_MASK           0x00000800
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_SHIFT          11
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: p8_tx_en_en [10:10] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_MASK       0x00000400
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_SHIFT      10
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_DEFAULT    0x00000001

/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: p8_rx_dv_en [09:09] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_MASK       0x00000200
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_SHIFT      9
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_DEFAULT    0x00000001

/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: port_en [08:00] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_MASK           0x000001ff
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_SHIFT          0
#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_DEFAULT        0x00000000

/***************************************************************************
 *AGGREGATE_LED_BLINK_RATE_CNTRL - Aggregate LED Blink Rate Control Register
 ***************************************************************************/
/* SWITCH_REG :: AGGREGATE_LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_MASK 0xffff0000
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT 16
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT 0x00000320

/* SWITCH_REG :: AGGREGATE_LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_MASK 0x0000ffff
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT 0
#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT 0x00000320

/***************************************************************************
 *SPARE_CNTRL - Spare Control Register
 ***************************************************************************/
/* SWITCH_REG :: SPARE_CNTRL :: spare_reg [31:00] */
#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_MASK                 0xffffffff
#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_SHIFT                0
#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_DEFAULT              0x00000000

/***************************************************************************
 *SWITCH_PHY_INTR_CNTRL - Switch PHY Interrupt Control Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_PHY_INTR_CNTRL :: reserved0 [31:08] */
#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_reserved0_MASK       0xffffff00
#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_reserved0_SHIFT      8

/* SWITCH_REG :: SWITCH_PHY_INTR_CNTRL :: phy_intr_pol_inv [07:00] */
#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_phy_intr_pol_inv_MASK 0x000000ff
#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_phy_intr_pol_inv_SHIFT 0
#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_phy_intr_pol_inv_DEFAULT 0x00000000

#endif /* #ifndef BCHP_SWITCH_REG_H__ */

/* End of File */