| /* |
| * Device Tree Source for the EMEV2 SoC |
| * |
| * Copyright (C) 2012 Renesas Solutions Corp. |
| * |
| * This file is licensed under the terms of the GNU General Public License |
| * version 2. This program is licensed "as is" without any warranty of any |
| * kind, whether express or implied. |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| / { |
| compatible = "renesas,emev2"; |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| gpio0 = &gpio0; |
| gpio1 = &gpio1; |
| gpio2 = &gpio2; |
| gpio3 = &gpio3; |
| gpio4 = &gpio4; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0>; |
| clock-frequency = <533000000>; |
| }; |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <1>; |
| clock-frequency = <533000000>; |
| }; |
| }; |
| |
| gic: interrupt-controller@e0020000 { |
| compatible = "arm,cortex-a9-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0xe0028000 0x1000>, |
| <0xe0020000 0x0100>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, |
| <0 121 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| clocks@e0110000 { |
| compatible = "renesas,emev2-smu"; |
| reg = <0xe0110000 0x10000>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| c32ki: c32ki { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| #clock-cells = <0>; |
| }; |
| pll3_fo: pll3_fo { |
| compatible = "fixed-factor-clock"; |
| clocks = <&c32ki>; |
| clock-div = <1>; |
| clock-mult = <7000>; |
| #clock-cells = <0>; |
| }; |
| usia_u0_sclkdiv: usia_u0_sclkdiv { |
| compatible = "renesas,emev2-smu-clkdiv"; |
| reg = <0x610 0>; |
| clocks = <&pll3_fo>; |
| #clock-cells = <0>; |
| }; |
| usib_u1_sclkdiv: usib_u1_sclkdiv { |
| compatible = "renesas,emev2-smu-clkdiv"; |
| reg = <0x65c 0>; |
| clocks = <&pll3_fo>; |
| #clock-cells = <0>; |
| }; |
| usib_u2_sclkdiv: usib_u2_sclkdiv { |
| compatible = "renesas,emev2-smu-clkdiv"; |
| reg = <0x65c 16>; |
| clocks = <&pll3_fo>; |
| #clock-cells = <0>; |
| }; |
| usib_u3_sclkdiv: usib_u3_sclkdiv { |
| compatible = "renesas,emev2-smu-clkdiv"; |
| reg = <0x660 0>; |
| clocks = <&pll3_fo>; |
| #clock-cells = <0>; |
| }; |
| usia_u0_sclk: usia_u0_sclk { |
| compatible = "renesas,emev2-smu-gclk"; |
| reg = <0x4a0 1>; |
| clocks = <&usia_u0_sclkdiv>; |
| #clock-cells = <0>; |
| }; |
| usib_u1_sclk: usib_u1_sclk { |
| compatible = "renesas,emev2-smu-gclk"; |
| reg = <0x4b8 1>; |
| clocks = <&usib_u1_sclkdiv>; |
| #clock-cells = <0>; |
| }; |
| usib_u2_sclk: usib_u2_sclk { |
| compatible = "renesas,emev2-smu-gclk"; |
| reg = <0x4bc 1>; |
| clocks = <&usib_u2_sclkdiv>; |
| #clock-cells = <0>; |
| }; |
| usib_u3_sclk: usib_u3_sclk { |
| compatible = "renesas,emev2-smu-gclk"; |
| reg = <0x4c0 1>; |
| clocks = <&usib_u3_sclkdiv>; |
| #clock-cells = <0>; |
| }; |
| sti_sclk: sti_sclk { |
| compatible = "renesas,emev2-smu-gclk"; |
| reg = <0x528 1>; |
| clocks = <&c32ki>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| timer@e0180000 { |
| compatible = "renesas,em-sti"; |
| reg = <0xe0180000 0x54>; |
| interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sti_sclk>; |
| clock-names = "sclk"; |
| }; |
| |
| uart0: serial@e1020000 { |
| compatible = "renesas,em-uart"; |
| reg = <0xe1020000 0x38>; |
| interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&usia_u0_sclk>; |
| clock-names = "sclk"; |
| }; |
| |
| uart1: serial@e1030000 { |
| compatible = "renesas,em-uart"; |
| reg = <0xe1030000 0x38>; |
| interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&usib_u1_sclk>; |
| clock-names = "sclk"; |
| }; |
| |
| uart2: serial@e1040000 { |
| compatible = "renesas,em-uart"; |
| reg = <0xe1040000 0x38>; |
| interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&usib_u2_sclk>; |
| clock-names = "sclk"; |
| }; |
| |
| uart3: serial@e1050000 { |
| compatible = "renesas,em-uart"; |
| reg = <0xe1050000 0x38>; |
| interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&usib_u3_sclk>; |
| clock-names = "sclk"; |
| }; |
| |
| pfc: pfc@e0140200 { |
| compatible = "renesas,pfc-emev2"; |
| reg = <0xe0140200 0x100>; |
| }; |
| |
| gpio0: gpio@e0050000 { |
| compatible = "renesas,em-gio"; |
| reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; |
| interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, |
| <0 68 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 32>; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| gpio1: gpio@e0050080 { |
| compatible = "renesas,em-gio"; |
| reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; |
| interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, |
| <0 70 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 32>; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| gpio2: gpio@e0050100 { |
| compatible = "renesas,em-gio"; |
| reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; |
| interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, |
| <0 72 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 32>; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| gpio3: gpio@e0050180 { |
| compatible = "renesas,em-gio"; |
| reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; |
| interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, |
| <0 74 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 32>; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| gpio4: gpio@e0050200 { |
| compatible = "renesas,em-gio"; |
| reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; |
| interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, |
| <0 76 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 31>; |
| #gpio-cells = <2>; |
| ngpios = <31>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
