/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Tue Dec  2 03:18:45 2014
 *                 Full Compile MD5 Checksum 3461841ff250f7118305e1f1650424cf
 *                   (minus title and desc)  
 *                 MD5 Checksum              92044aba65695bbffdeefc8d096b8587
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008008
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__
#define BCHP_DDR34_PHY_CONTROL_REGS_0_H__

/***************************************************************************
 *DDR34_PHY_CONTROL_REGS_0 - DDR34 Address/Comand control registers
 ***************************************************************************/
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION   0x00506000 /* Address & Control revision register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS 0x00506004 /* PHY PLL status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG 0x00506008 /* PHY PLL configuration register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1 0x0050600c /* PHY PLL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2 0x00506010 /* PHY PLL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3 0x00506014 /* PHY PLL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x00506018 /* PHY PLL integer divider register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER 0x0050601c /* PHY PLL fractional divider register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL 0x00506020 /* PHY PLL spread spectrum control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT 0x00506024 /* PHY PLL spread spectrum limit register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL 0x00506028 /* Aux Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x0050602c /* Idle mode pad control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0 0x00506030 /* Idle mode pad enable register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1 0x00506034 /* Idle mode pad enable register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x00506038 /* Drive strength control for all pads except CK_P, CK_N, CS, ODT and PAR */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T 0x0050603c /* Drive strength control for signals that are 1T when in 2T mode -- CS, ODT and PAR */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL 0x00506040 /* pad rx and tx characteristics control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T 0x00506044 /* pad rx and tx characteristics control register for signals that are 1T when in 2T mode -- CS, ODT and PAR */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM    0x00506048 /* Receiver trim */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG 0x0050604c /* DRAM configuration register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1 0x00506050 /* DRAM timing register #1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2 0x00506054 /* DRAM timing register #2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3 0x00506058 /* DRAM timing register #3 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4 0x0050605c /* DRAM timing register #4 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x00506060 /* PHY VDL calibration control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1 0x00506064 /* PHY VDL calibration status register #1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2 0x00506068 /* PHY VDL calibration status register #2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL 0x0050606c /* PHY VDL delay monitoring control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF 0x00506070 /* PHY VDL delay monitoring reference register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS 0x00506074 /* PHY VDL delay monitoring status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE 0x00506078 /* PHY VDL delay monitoring override register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL 0x0050607c /* PHY VDL delay monitoring output control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS 0x00506080 /* PHY VDL delay monitoring output status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR 0x00506084 /* PHY VDL delay monitoring output status clear register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00 0x00506088 /* DDR interface signal AD[00] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01 0x0050608c /* DDR interface signal AD[01] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02 0x00506090 /* DDR interface signal AD[02] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03 0x00506094 /* DDR interface signal AD[03] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04 0x00506098 /* DDR interface signal AD[04] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05 0x0050609c /* DDR interface signal AD[05] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06 0x005060a0 /* DDR interface signal AD[06] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07 0x005060a4 /* DDR interface signal AD[07] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08 0x005060a8 /* DDR interface signal AD[08] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09 0x005060ac /* DDR interface signal AD[09] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10 0x005060b0 /* DDR interface signal AD[10] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11 0x005060b4 /* DDR interface signal AD[11] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12 0x005060b8 /* DDR interface signal AD[12] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13 0x005060bc /* DDR interface signal AD[13] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14 0x005060c0 /* DDR interface signal AD[14] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15 0x005060c4 /* DDR interface signal AD[15] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0 0x005060c8 /* DDR interface signal BA[0] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1 0x005060cc /* DDR interface signal BA[1] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2 0x005060d0 /* DDR interface signal BA[2] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0 0x005060d4 /* DDR interface signal AUX[0] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1 0x005060d8 /* DDR interface signal AUX[1] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2 0x005060dc /* DDR interface signal AUX[2] VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0 0x005060e0 /* DDR interface signal CS0 VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1 0x005060e4 /* DDR interface signal CS1 VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR 0x005060e8 /* DDR interface signal PAR VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N 0x005060ec /* DDR interface signal RAS_N VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N 0x005060f0 /* DDR interface signal CAS_N VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE 0x005060f4 /* DDR interface signal CKE0 VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N 0x005060f8 /* DDR interface signal RST_N VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT 0x005060fc /* DDR interface signal ODT0 VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N 0x00506100 /* DDR interface signal WE_N VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK 0x00506104 /* DDR interface signal DDR_CK VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL 0x00506108 /* DDR interface signal Write Leveling CLK VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL 0x0050610c /* DDR interface signal Write Leveling Capture Enable VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY 0x00506110 /* GDDR5 command interface delay stage control */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL 0x00506114 /* Update VDL control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1 0x00506118 /* Update VDL snoop control register #1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2 0x0050611c /* Update VDL snoop control register #2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1 0x00506120 /* DRAM Command Register #1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1 0x00506124 /* DRAM AUX_N Command Register #1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2 0x00506128 /* DRAM Command Register #2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2 0x0050612c /* DRAM AUX_N Command Register #2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3 0x00506130 /* DRAM Command Register #3 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3 0x00506134 /* DRAM AUX_N Command Register #3 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4 0x00506138 /* DRAM Command Register #4 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4 0x0050613c /* DRAM AUX_N Command Register #4 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER 0x00506140 /* DRAM Command Timer Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0  0x00506144 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1  0x00506148 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2  0x0050614c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3  0x00506150 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4  0x00506154 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5  0x00506158 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6  0x0050615c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7  0x00506160 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8  0x00506164 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15 0x00506168 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63 0x0050616c /* LPDDR Mode Register 63 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR 0x00506170 /* DDR4 Alert status clear register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS 0x00506174 /* DDR4 Alert status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI  0x00506178 /* DDR4 Alert DFI BL mask */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL 0x0050617c /* GDDR5 CA playback control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0 0x00506180 /* LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1 0x00506184 /* LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL 0x00506188 /* Write leveling control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS 0x0050618c /* Write leveling status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL 0x00506190 /* Read enable test cycle control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS 0x00506194 /* Read enable test cycle status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x00506198 /* Virtual VTT Control and Status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x0050619c /* Virtual VTT Control and Status register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x005061a0 /* Virtual VTT Connections register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x005061a4 /* Virtual VTT Override register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x005061a8 /* VREF DAC Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x005061ac /* PhyBist Control Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x005061b0 /* PhyBist Seed Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK 0x005061b4 /* PhyBist Command/Address Bus Mask */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1 0x005061b8 /* PhyBist Data Bus Mask #1 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2 0x005061bc /* PhyBist Data Bus Mask #2 */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x005061c0 /* PhyBist General Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x005061c4 /* PhyBist Per-Bit Control Pad Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS 0x005061c8 /* PhyBist Byte Lane #0 Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS 0x005061cc /* PhyBist Byte Lane #1 Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS 0x005061d0 /* PhyBist Byte Lane #2 Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS 0x005061d4 /* PhyBist Byte Lane #3 Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS 0x005061d8 /* PhyBist Byte Lane #4 (ECC) Status Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x005061dc /* Standby Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x005061e0 /* Freeze-on-error enable register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL 0x005061e4 /* Debug Mux Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL  0x005061e8 /* DFI Interface Ownership Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL 0x005061ec /* Write ODT Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL 0x005061f0 /* ABI and PAR Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL     0x005061f4 /* ZQ Calibration Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2    0x005061f8 /* ZQ Calibration Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL   0x005061fc /* COMR Calibration Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL 0x00506200 /* Ring-Osc control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS 0x00506204 /* Ring-Osc count register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL 0x00506208 /* Drive strength control register for CK_P and CK_N */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL 0x0050620c /* LDO Comparator Control register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS 0x00506210 /* Byte-lane alignment mask register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE 0x00506214 /* Clock Idle Register */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG 0x00506218 /* Address and Control Spare register */

/***************************************************************************
 *REVISION - Address & Control revision register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xfe000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     25

/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: PERFORMANCE [24:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_MASK    0x01800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_PERFORMANCE_SHIFT   23

/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20

/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19

/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16

/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x000000f0

/* DDR34_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000003

/***************************************************************************
 *PLL_STATUS - PHY PLL status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xfffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   17

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   16

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_8X [15:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_MASK  0x00008000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_8X_SHIFT 15

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [14:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00004000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 14

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_2X [13:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_MASK  0x00002000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_2X_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0

/***************************************************************************
 *PLL_CONFIG - PHY PLL configuration register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_DVDD1P0V_OUTPUT_V [31:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_OUTPUT_V_MASK 0xc0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_OUTPUT_V_SHIFT 30
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_OUTPUT_V_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_AVDD1P0V_OUTPUT_V [29:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_OUTPUT_V_MASK 0x30000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_OUTPUT_V_SHIFT 28
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_OUTPUT_V_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_DVDD1P0V_BLEEDING_I [27:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_BLEEDING_I_MASK 0x0c000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_BLEEDING_I_SHIFT 26
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_DVDD1P0V_BLEEDING_I_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_AVDD1P0V_BLEEDING_I [25:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_BLEEDING_I_MASK 0x03000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_BLEEDING_I_SHIFT 24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_AVDD1P0V_BLEEDING_I_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_PWRDOWN [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_PWRDOWN_MASK 0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_PWRDOWN_SHIFT 23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_BIAS20 [22:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS20_MASK 0x00600000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS20_SHIFT 21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS20_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: CK_LDO_BIAS [20:19] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_MASK  0x00180000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_SHIFT 19
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PLL_LDO_PWRDOWN [18:18] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_PWRDOWN_MASK 0x00040000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_PWRDOWN_SHIFT 18
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PLL_LDO_PWRDOWN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: HOLD [17:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_MASK         0x00020000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_SHIFT        17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_HOLD_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ENABLE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_MASK       0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_SHIFT      16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_DEFAULT    0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [15:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0x0000c000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   14

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: FB_OFFSET [13:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_MASK    0x00003f00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_SHIFT   8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   6

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ENABLE_EXT_CTRL [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_EXT_CTRL_MASK 0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_EXT_CTRL_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ENABLE_EXT_CTRL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ISO_OUT [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_OUT_MASK      0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_OUT_SHIFT     3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_OUT_DEFAULT   0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: ISO_IN [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_IN_MASK       0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_IN_SHIFT      2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_ISO_IN_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000001

/***************************************************************************
 *PLL_CONTROL1 - PHY PLL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_MASK  0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KP [09:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_MASK       0x000003c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_SHIFT      6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KP_DEFAULT    0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KI [05:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_MASK       0x00000038
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_SHIFT      3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KI_DEFAULT    0x00000004

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL1 :: I_KA [02:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_MASK       0x00000007
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL1_I_KA_DEFAULT    0x00000000

/***************************************************************************
 *PLL_CONTROL2 - PHY PLL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: REF_ALT_OFFS [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_REF_ALT_OFFS_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_REF_ALT_OFFS_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_REF_ALT_OFFS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_RANGE_CONTROL_FOR_LOW [30:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_LOW_MASK 0x40000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_LOW_SHIFT 30
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_LOW_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: AUX_CTRL [29:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_AUX_CTRL_MASK   0x20000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_AUX_CTRL_SHIFT  29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_AUX_CTRL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_MASK  0x08000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_SHIFT 27
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: PWM_RATE [23:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_MASK   0x00c00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_SHIFT  22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_MODE [21:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_MASK  0x00300000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: VCO_RANGE_CONTROL_FOR_HIGH [19:19] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_HIGH_MASK 0x00080000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_HIGH_SHIFT 19
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_VCO_RANGE_CONTROL_FOR_HIGH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DITHER_DISABLE [18:18] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DITHER_DISABLE_MASK 0x00040000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DITHER_DISABLE_SHIFT 18
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DITHER_DISABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_SHIFT 14
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: STAT_RESET [13:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_MASK 0x00002000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_SHIFT 13
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL2 :: DCO_CTRL_BYP [11:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYP_MASK 0x00000fff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL2_DCO_CTRL_BYP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CONTROL3 - PHY PLL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000

/***************************************************************************
 *PLL_DIVIDERS - PHY PLL integer divider register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xf0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 28

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: MDIV [27:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_MASK       0x0ff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_SHIFT      20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_MDIV_DEFAULT    0x00000004

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved1 [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_MASK  0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved1_SHIFT 16

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [15:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x0000f000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved2 [11:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_MASK  0x00000c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved2_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_INT [09:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_MASK   0x000003ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_SHIFT  0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000020

/***************************************************************************
 *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_reserved0_SHIFT 20

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SS_CONTROL - PHY PLL spread spectrum control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved0_SHIFT 20

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: reserved1 [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_reserved1_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved0 [31:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_MASK  0xfc000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved0_SHIFT 26

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_MASK  0x03fffff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PLL_SS_LIMIT :: reserved1 [03:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_MASK  0x0000000f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PLL_SS_LIMIT_reserved1_SHIFT 0

/***************************************************************************
 *AUX_CONTROL - Aux Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xffffffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  5

/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: AUX0_IS_ODT [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_AUX0_IS_ODT_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_AUX0_IS_ODT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_AUX0_IS_ODT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: PAR_IS_ODT [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_PAR_IS_ODT_MASK  0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_PAR_IS_ODT_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_PAR_IS_ODT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: IS_CS [02:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_MASK       0x00000007
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AUX_CONTROL_IS_CS_DEFAULT    0x00000000

/***************************************************************************
 *IDLE_PAD_CONTROL - Idle mode pad control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [29:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x3fffff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 8

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved_for_eco1 [07:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_MASK 0x000000f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_MASK  0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_MASK   0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_SHIFT  2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000

/***************************************************************************
 *IDLE_PAD_ENABLE0 - Idle mode pad enable register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: reserved0 [31:11] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_MASK 0xfffff800
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_reserved0_SHIFT 11

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *IDLE_PAD_ENABLE1 - Idle mode pad enable register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_reserved0_SHIFT 22

/* DDR34_PHY_CONTROL_REGS_0 :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *DRIVE_PAD_CTL - Drive strength control for all pads except CK_P, CK_N, CS, ODT and PAR
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 30

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x00000010

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x00000010

/***************************************************************************
 *DRIVE_PAD_CTL_2T - Drive strength control for signals that are 1T when in 2T mode -- CS, ODT and PAR
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_reserved0_SHIFT 30

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_PD_STRENGTH_DEFAULT 0x00000010

/* DDR34_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL_2T :: ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_2T_ND_STRENGTH_DEFAULT 0x00000010

/***************************************************************************
 *STATIC_PAD_CTL - pad rx and tx characteristics control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved0 [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved0_SHIFT 31

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: TX_SLEW [30:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_SLEW_MASK  0x60000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_SLEW_SHIFT 29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: AUTO_OEB [28:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_MASK 0x10000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_SHIFT 28
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_GDDR5 [27:27] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x08000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 27
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_LPDDR [26:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x04000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 26
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CLK0 [25:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x02000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_ODT [24:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x01000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_PAR [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_BA [22:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_MASK  0x00400000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_SHIFT 22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX2 [21:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00200000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX1 [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_AUX0 [19:19] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00080000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 19
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_CS1 [18:18] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00040000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 18
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A15 [17:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00020000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A14 [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A13 [15:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00008000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_SHIFT 15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A12 [14:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00004000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_SHIFT 14
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A11 [13:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00002000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_SHIFT 13
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A10 [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: IDDQ_A09 [11:11] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000800
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_SHIFT 11
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved1 [10:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_MASK 0x00000400
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved1_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_MASK  0x000003f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: reserved2 [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_reserved2_SHIFT 3

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_MASK  0x00000007
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000

/***************************************************************************
 *STATIC_PAD_CTL_2T - pad rx and tx characteristics control register for signals that are 1T when in 2T mode -- CS, ODT and PAR
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: reserved0 [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved0_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved0_SHIFT 31

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: TX_SLEW [30:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_SLEW_MASK 0x60000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_SLEW_SHIFT 29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_SLEW_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: reserved1 [28:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved1_MASK 0x1ffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved1_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: TX_MODE [09:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_MODE_MASK 0x000003f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_MODE_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_TX_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STATIC_PAD_CTL_2T :: reserved2 [03:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved2_MASK 0x0000000f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STATIC_PAD_CTL_2T_reserved2_SHIFT 0

/***************************************************************************
 *RX_TRIM - Receiver trim
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: reserved0 [31:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_reserved0_MASK       0xffffc000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_reserved0_SHIFT      14

/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: DF_LSTRIM [13:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_LSTRIM_MASK       0x00003c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_LSTRIM_SHIFT      10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_LSTRIM_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: DF_ITRIM [09:07] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_ITRIM_MASK        0x00000380
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_ITRIM_SHIFT       7
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_DF_ITRIM_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: SE_LSTRIM [06:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_LSTRIM_MASK       0x00000078
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_LSTRIM_SHIFT      3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_LSTRIM_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RX_TRIM :: SE_ITRIM [02:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_ITRIM_MASK        0x00000007
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_ITRIM_SHIFT       0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RX_TRIM_SE_ITRIM_DEFAULT     0x00000000

/***************************************************************************
 *DRAM_CONFIG - DRAM configuration register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: INIT_MODE [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved0 [30:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_MASK   0x70000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved0_SHIFT  28

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_SHIFT 27
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS16 [25:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_MASK       0x02000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_SHIFT      25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS16_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BUS8 [24:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_MASK        0x01000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_SHIFT       24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BUS8_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: reserved1 [23:18] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_MASK   0x00fc0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_reserved1_SHIFT  18

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: CRC_ENABLED [17:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_CRC_ENABLED_MASK 0x00020000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_CRC_ENABLED_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_CRC_ENABLED_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: DDR4_GEARDOWN_ENABLE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: EDC_MODE [15:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_MASK    0x00008000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_SHIFT   15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: RDQS_MODE [14:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_MASK   0x00004000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_SHIFT  14
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: GROUP_BITS [13:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_MASK  0x00003000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: BANK_BITS [11:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_MASK   0x00000c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_SHIFT  10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: COL_BITS [09:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_MASK    0x00000300
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_SHIFT   8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: ROW_BITS [07:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_MASK    0x000000f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_SHIFT   4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_MASK   0x0000000f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_SHIFT  0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000

/***************************************************************************
 *DRAM_TIMING1 - DRAM timing register #1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRAS [31:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_MASK       0xff000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_SHIFT      24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRAS_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRRD [23:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_MASK       0x00ff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_SHIFT      16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRRD_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRP [15:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_MASK        0x0000ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_SHIFT       8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRP_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING1 :: TRCD [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_MASK       0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING1_TRCD_DEFAULT    0x00000000

/***************************************************************************
 *DRAM_TIMING2 - DRAM timing register #2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TRTP [31:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_MASK       0xff000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_SHIFT      24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TRTP_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TWR [23:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_MASK        0x00ff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_SHIFT       16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TWR_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCWL [15:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_MASK       0x0000ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_SHIFT      8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCWL_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING2 :: TCAS [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_MASK       0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING2_TCAS_DEFAULT    0x00000000

/***************************************************************************
 *DRAM_TIMING3 - DRAM timing register #3
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: reserved0 [31:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_MASK  0xf0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_reserved0_SHIFT 28

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TCAL [27:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_MASK       0x0ff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_SHIFT      20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TCAL_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRTW [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_MASK       0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_SHIFT      16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRTW_DEFAULT    0x00000004

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TWTR [15:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_MASK       0x0000f000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_SHIFT      12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TWTR_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING3 :: TRFC [11:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_MASK       0x00000fff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING3_TRFC_DEFAULT    0x00000000

/***************************************************************************
 *DRAM_TIMING4 - DRAM timing register #4
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DRAM_TIMING4 :: temp [31:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_MASK       0xffffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DRAM_TIMING4_temp_DEFAULT    0x00000000

/***************************************************************************
 *VDL_CALIBRATE - PHY VDL calibration control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved_for_eco1 [09:07] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_MASK 0x00000380
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_SHIFT 7
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_FAST [06:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FAST_MASK 0x00000040
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FAST_SHIFT 6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FAST_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved0_SHIFT 18

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_reserved1_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001

/***************************************************************************
 *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved0_SHIFT 22

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_reserved1_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved0 [31:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_MASK 0xff000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved0_SHIFT 24

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: INTERVAL [23:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x00ffff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_reserved1_SHIFT 4

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved0 [31:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved0_SHIFT 22

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: reserved1 [11:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_reserved1_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved0 [31:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_MASK 0xff000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved0_SHIFT 24

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [23:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: reserved1 [15:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_MASK 0x0000c000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_reserved1_SHIFT 14

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [13:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: ERROR [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_ERROR_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_ERROR_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: PAUSED [02:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_PAUSED_MASK 0x00000006
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_PAUSED_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_PAUSED_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_STATUS :: BUSY [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_BUSY_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_BUSY_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_STATUS_BUSY_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: reserved1 [15:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000ffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 5

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OVERRIDE :: ADJ [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000

/***************************************************************************
 *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_DDR_CK - DDR interface signal DDR_CK VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CONTROL_DDR_CK :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CONTROL_DDR_CK_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_MASK    0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_SHIFT   31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_reserved2_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *CMD_CYC_DLY - GDDR5 command interface delay stage control
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: reserved0 [31:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_reserved0_MASK   0xffffffc0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_reserved0_SHIFT  6

/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: CKE [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CKE_MASK         0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CKE_SHIFT        5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CKE_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: WE_N [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_WE_N_MASK        0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_WE_N_SHIFT       4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_WE_N_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: CAS_N [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CAS_N_MASK       0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CAS_N_SHIFT      3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CAS_N_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: RAS_N [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_RAS_N_MASK       0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_RAS_N_SHIFT      2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_RAS_N_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CMD_CYC_DLY :: CS_N [01:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CS_N_MASK        0x00000003
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CS_N_SHIFT       0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CMD_CYC_DLY_CS_N_DEFAULT     0x00000000

/***************************************************************************
 *UPDATE_VDL - Update VDL control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_MASK    0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved0_SHIFT   10

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: MODE [09:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_MASK         0x000003f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_SHIFT        4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_MODE_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: reserved1 [03:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_MASK    0x0000000c
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_reserved1_SHIFT   2

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_MASK       0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_ENABLE_DEFAULT    0x00000000

/***************************************************************************
 *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved0 [31:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_MASK 0xe0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved0_SHIFT 29

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: MASK [28:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_MASK  0x1ff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved1 [19:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_MASK 0x000e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved1_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: CMD [16:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_MASK   0x0001ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_SHIFT  8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: reserved2 [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_MASK 0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_reserved2_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP1 :: ENABLE [05:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x0000003f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved0 [31:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_MASK 0xe0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved0_SHIFT 29

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: MASK [28:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_MASK  0x1ff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved1 [19:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_MASK 0x000e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved1_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: CMD [16:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_MASK   0x0001ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_SHIFT  8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: reserved2 [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_MASK 0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_reserved2_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: UPDATE_VDL_SNOOP2 :: ENABLE [05:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x0000003f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *COMMAND_REG1 - DRAM Command Register #1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: MCP [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_MASK        0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_SHIFT       31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_MCP_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CS [30:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_MASK         0x60000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_SHIFT        29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CS_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AUX [28:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_MASK        0x1f000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_SHIFT       24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AUX_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: ACT [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_MASK        0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_SHIFT       23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_ACT_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: WE [22:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_MASK         0x00400000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_SHIFT        22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_WE_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: CAS [21:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_MASK        0x00200000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_SHIFT       21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_CAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: RAS [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_MASK        0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_SHIFT       20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_RAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: BA [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_MASK         0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_BA_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG1 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_MASK         0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_SHIFT        0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG1_AD_DEFAULT      0x00000000

/***************************************************************************
 *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: reserved0 [31:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_MASK 0xffffffc0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_reserved0_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: AD16 [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AD16_MASK   0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AD16_SHIFT  5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AD16_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG1 :: AUX [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_MASK    0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000

/***************************************************************************
 *COMMAND_REG2 - DRAM Command Register #2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: MCP [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_MASK        0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_SHIFT       31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_MCP_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CS [30:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_MASK         0x60000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_SHIFT        29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CS_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AUX [28:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_MASK        0x1f000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_SHIFT       24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AUX_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: ACT [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_MASK        0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_SHIFT       23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_ACT_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: WE [22:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_MASK         0x00400000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_SHIFT        22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_WE_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: CAS [21:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_MASK        0x00200000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_SHIFT       21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_CAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: RAS [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_MASK        0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_SHIFT       20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_RAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: BA [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_MASK         0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_BA_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG2 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_MASK         0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_SHIFT        0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG2_AD_DEFAULT      0x00000000

/***************************************************************************
 *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: reserved0 [31:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_MASK 0xffffffc0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_reserved0_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: AD16 [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AD16_MASK   0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AD16_SHIFT  5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AD16_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG2 :: AUX [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_MASK    0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000

/***************************************************************************
 *COMMAND_REG3 - DRAM Command Register #3
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: MCP [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_MASK        0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_SHIFT       31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_MCP_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CS [30:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_MASK         0x60000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_SHIFT        29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CS_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AUX [28:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_MASK        0x1f000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_SHIFT       24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AUX_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: ACT [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_MASK        0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_SHIFT       23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_ACT_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: WE [22:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_MASK         0x00400000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_SHIFT        22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_WE_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: CAS [21:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_MASK        0x00200000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_SHIFT       21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_CAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: RAS [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_MASK        0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_SHIFT       20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_RAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: BA [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_MASK         0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_BA_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG3 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_MASK         0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_SHIFT        0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG3_AD_DEFAULT      0x00000000

/***************************************************************************
 *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: reserved0 [31:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_MASK 0xffffffc0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_reserved0_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: AD16 [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AD16_MASK   0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AD16_SHIFT  5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AD16_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG3 :: AUX [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_MASK    0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000

/***************************************************************************
 *COMMAND_REG4 - DRAM Command Register #4
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: MCP [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_MASK        0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_SHIFT       31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_MCP_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CS [30:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_MASK         0x60000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_SHIFT        29
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CS_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AUX [28:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_MASK        0x1f000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_SHIFT       24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AUX_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: ACT [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_MASK        0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_SHIFT       23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_ACT_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: WE [22:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_MASK         0x00400000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_SHIFT        22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_WE_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: CAS [21:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_MASK        0x00200000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_SHIFT       21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_CAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: RAS [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_MASK        0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_SHIFT       20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_RAS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: BA [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_MASK         0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_BA_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG4 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_MASK         0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_SHIFT        0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG4_AD_DEFAULT      0x00000000

/***************************************************************************
 *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: reserved0 [31:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_MASK 0xffffffc0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_reserved0_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: AD16 [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AD16_MASK   0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AD16_SHIFT  5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AD16_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_AUX_REG4 :: AUX [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_MASK    0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000

/***************************************************************************
 *COMMAND_REG_TIMER - DRAM Command Timer Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: reserved0 [31:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_reserved0_SHIFT 16

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f

/* DDR34_PHY_CONTROL_REGS_0 :: COMMAND_REG_TIMER :: COUNT [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000

/***************************************************************************
 *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG0 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG0_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG1 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG1_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG2 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG2_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG3 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG3_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG4 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG4_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG5 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG5_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG6 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG6_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG7 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG7_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved0_SHIFT    21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_MASK         0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_SHIFT        16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_VALID_DEFAULT      0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG8 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_MASK            0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_SHIFT           0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG8_AD_DEFAULT         0x00000000

/***************************************************************************
 *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_MASK    0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved0_SHIFT   21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_MASK        0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_SHIFT       16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_VALID_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG15 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_MASK           0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_SHIFT          0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG15_AD_DEFAULT        0x00000000

/***************************************************************************
 *MODE_REG63 - LPDDR Mode Register 63
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_MASK    0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved0_SHIFT   21

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: reserved_for_eco1 [20:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_MASK 0x001e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: VALID [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_MASK        0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_SHIFT       16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_VALID_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: MODE_REG63 :: AD [15:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_MASK           0x0000ffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_SHIFT          0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_MODE_REG63_AD_DEFAULT        0x00000000

/***************************************************************************
 *ALERT_CLEAR - DDR4 Alert status clear register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: reserved0 [31:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_MASK   0xfffffffe
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_reserved0_SHIFT  1

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_CLEAR :: CLEAR [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_MASK       0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_CLEAR_CLEAR_DEFAULT    0x00000000

/***************************************************************************
 *ALERT_STATUS - DDR4 Alert status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: reserved0 [31:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_MASK  0xffffe000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved0_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL4_STATE [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_STATE_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_STATE_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_STATE_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL3_STATE [11:11] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_STATE_MASK  0x00000800
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_STATE_SHIFT 11
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_STATE_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL2_STATE [10:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_STATE_MASK  0x00000400
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_STATE_SHIFT 10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_STATE_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL1_STATE [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_STATE_MASK  0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_STATE_SHIFT 9
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_STATE_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL0_STATE [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_STATE_MASK  0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_STATE_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_STATE_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: reserved1 [07:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved1_MASK  0x000000e0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_reserved1_SHIFT 5

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL4_ALERT [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_ALERT_MASK  0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_ALERT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL4_ALERT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL3_ALERT [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_ALERT_MASK  0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_ALERT_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL3_ALERT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL2_ALERT [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_ALERT_MASK  0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_ALERT_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL2_ALERT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL1_ALERT [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_ALERT_MASK  0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_ALERT_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL1_ALERT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_STATUS :: BL0_ALERT [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_ALERT_MASK  0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_ALERT_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_STATUS_BL0_ALERT_DEFAULT 0x00000000

/***************************************************************************
 *ALERT_DFI - DDR4 Alert DFI BL mask
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_DFI :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_reserved0_MASK     0xffffffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_reserved0_SHIFT    5

/* DDR34_PHY_CONTROL_REGS_0 :: ALERT_DFI :: MASK [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_MASK_MASK          0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_MASK_SHIFT         0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ALERT_DFI_MASK_DEFAULT       0x00000000

/***************************************************************************
 *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000

/***************************************************************************
 *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1)
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000

/***************************************************************************
 *CA_PLAYBACK_STATUS1 - LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3)
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_SHIFT 31
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_VALID_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved0 [30:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_MASK 0x7c000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved0_SHIFT 26

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA1 [25:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_MASK 0x03ff0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: reserved1 [15:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_MASK 0x0000fc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_reserved1_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: CA_PLAYBACK_STATUS1 :: DATA0 [09:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000003ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CA_PLAYBACK_STATUS1_DATA0_DEFAULT 0x00000000

/***************************************************************************
 *WRITE_LEVELING_CONTROL - Write leveling control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved0_SHIFT 20

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved_for_eco1 [19:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_MASK 0x000f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: reserved2 [07:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_MASK 0x000000f8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_reserved2_SHIFT 3

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *WRITE_LEVELING_STATUS - Write leveling status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved0_SHIFT 14

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: EDC [13:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_SHIFT 9
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_reserved1_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_LEVELING_STATUS :: VALID [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000

/***************************************************************************
 *READ_ENABLE_CONTROL - Read enable test cycle control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved0_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: SELECT [11:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: reserved_for_eco1 [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_MASK 0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_SHIFT 6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: CS_N [05:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: DQS [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *READ_ENABLE_STATUS - Read enable test cycle status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved0_SHIFT 20

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: DATA [19:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_MASK 0x000ff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved1 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved1_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL4_STATUS [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_MASK 0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL4_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL3_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL2_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: reserved2 [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_reserved2_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: READ_ENABLE_STATUS :: VALID [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000

/***************************************************************************
 *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000

/***************************************************************************
 *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: READY [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000

/***************************************************************************
 *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff

/***************************************************************************
 *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31

/* DDR34_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff

/***************************************************************************
 *VREF_DAC_CONTROL - VREF DAC Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: AUX_GT_INT [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [19:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x000e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [16:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00010000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN3 [15:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_MASK   0x00008000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_SHIFT  15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN2 [14:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_MASK   0x00004000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_SHIFT  14
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020

/* DDR34_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020

/***************************************************************************
 *PHYBIST_CNTRL - PhyBist Control Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 30

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: PATTERN_SEL [29:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_PATTERN_SEL_MASK 0x30000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_PATTERN_SEL_SHIFT 28
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_PATTERN_SEL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [27:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x0f000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco1 [23:23] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco1_MASK 0x00800000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco1_SHIFT 23
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved_for_eco2 [19:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_MASK 0x000e0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_SHIFT 17
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved_for_eco2_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved3 [11:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved3_MASK 0x00000c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved3_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: SSO [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_MASK       0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_SHIFT      6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_SSO_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: LENGTH [05:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_MASK    0x00000030
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_SHIFT   4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: MODE [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_MASK      0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_SHIFT     1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_MODE_DEFAULT   0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_MASK    0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PHYBIST_SEED - PhyBist Seed Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: SEED [31:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_MASK       0xffffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_SEED_SEED_DEFAULT    0xba5eba11

/***************************************************************************
 *PHYBIST_CA_MASK - PhyBist Command/Address Bus Mask
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CA_MASK :: MASK [31:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK_MASK_MASK    0xffffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK_MASK_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CA_MASK_MASK_DEFAULT 0x00000000

/***************************************************************************
 *PHYBIST_DQ_MASK1 - PhyBist Data Bus Mask #1
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK1 :: MASK [31:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1_MASK_MASK   0xffffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1_MASK_SHIFT  0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK1_MASK_DEFAULT 0x00000000

/***************************************************************************
 *PHYBIST_DQ_MASK2 - PhyBist Data Bus Mask #2
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: reserved0 [31:17] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved0_MASK 0xfffe0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved0_SHIFT 17

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: EDC_MASK [16:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_EDC_MASK_MASK 0x0001f000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_EDC_MASK_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_EDC_MASK_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: reserved1 [11:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved1_MASK 0x00000e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_reserved1_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: DM_MASK [08:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DM_MASK_MASK 0x000001f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DM_MASK_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DM_MASK_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_MASK2 :: DQ_MASK [03:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DQ_MASK_MASK 0x0000000f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DQ_MASK_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_DQ_MASK2_DQ_MASK_DEFAULT 0x00000000

/***************************************************************************
 *PHYBIST_STATUS - PhyBist General Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_PASS [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_PASS_SHIFT 3

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_PASS [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_PASS_SHIFT 2

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: DAT_DONE [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_DAT_DONE_SHIFT 1

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: CTL_DONE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_STATUS_CTL_DONE_SHIFT 0

/***************************************************************************
 *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 31

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0

/***************************************************************************
 *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: EDC [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_MASK  0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_EDC_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DM [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_MASK   0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DM_SHIFT  8

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL0_STATUS :: DQ [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_MASK   0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL0_STATUS_DQ_SHIFT  0

/***************************************************************************
 *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: EDC [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_MASK  0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_EDC_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DM [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_MASK   0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DM_SHIFT  8

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL1_STATUS :: DQ [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_MASK   0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL1_STATUS_DQ_SHIFT  0

/***************************************************************************
 *PHYBIST_BL2_STATUS - PhyBist Byte Lane #2 Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_MASK 0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: EDC [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_MASK  0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_EDC_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DM [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_MASK   0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DM_SHIFT  8

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL2_STATUS :: DQ [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_MASK   0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL2_STATUS_DQ_SHIFT  0

/***************************************************************************
 *PHYBIST_BL3_STATUS - PhyBist Byte Lane #3 Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_MASK 0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: EDC [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_MASK  0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_EDC_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DM [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_MASK   0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DM_SHIFT  8

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL3_STATUS :: DQ [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_MASK   0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL3_STATUS_DQ_SHIFT  0

/***************************************************************************
 *PHYBIST_BL4_STATUS - PhyBist Byte Lane #4 (ECC) Status Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_MASK 0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_reserved0_SHIFT 10

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: EDC [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_MASK  0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_EDC_SHIFT 9

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DM [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_MASK   0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DM_SHIFT  8

/* DDR34_PHY_CONTROL_REGS_0 :: PHYBIST_BL4_STATUS :: DQ [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_MASK   0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_PHYBIST_BL4_STATUS_DQ_SHIFT  0

/***************************************************************************
 *STANDBY_CONTROL - Standby Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xffffffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 5

/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: PHY_STANDBY [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PHY_STANDBY_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PHY_STANDBY_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_PHY_STANDBY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: FORCE_CKE_RST_N [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_FORCE_CKE_RST_N_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_FORCE_CKE_RST_N_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_FORCE_CKE_RST_N_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: RST_N [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_MASK   0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_SHIFT  2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: CKE [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_MASK     0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_SHIFT    1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_CKE_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: BIT_PIPE_RESET [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_BIT_PIPE_RESET_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_BIT_PIPE_RESET_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_STANDBY_CONTROL_BIT_PIPE_RESET_DEFAULT 0x00000001

/***************************************************************************
 *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000

/***************************************************************************
 *DEBUG_MUX_CONTROL - Debug Mux Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_MASK 0xfffff800
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved0_SHIFT 11

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_MASK 0x000000c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_reserved1_SHIFT 6

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DFI_CNTRL - DFI Interface Ownership Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: reserved0 [31:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_MASK     0xfffffc00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_reserved0_SHIFT    10

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: SELF_REFRESH_CS1 [09:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS1_MASK 0x00000200
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS1_SHIFT 9
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS1_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: SELF_REFRESH_CS0 [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS0_MASK 0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS0_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_SELF_REFRESH_CS0_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS1 [07:07] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_MASK       0x00000080
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_SHIFT      7
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS1_DEFAULT    0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CS0 [06:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_MASK       0x00000040
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_SHIFT      6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CS0_DEFAULT    0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_RST_N [05:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_MASK     0x00000020
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_SHIFT    5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_RST_N_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CKE1 [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE1_MASK      0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE1_SHIFT     4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE1_DEFAULT   0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: DFI_CKE0 [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE0_MASK      0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE0_SHIFT     3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_DFI_CKE0_DEFAULT   0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_ENABLE [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_MASK    0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_SHIFT   2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ACK_STATUS [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_MASK    0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_SHIFT   1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: DFI_CNTRL :: ASSERT_REQ [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_MASK    0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001

/***************************************************************************
 *WRITE_ODT_CNTRL - Write ODT Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: reserved0 [31:29] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_MASK 0xe0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved0_SHIFT 29

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_FORCE_VALUE [28:28] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_MASK 0x10000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_SHIFT 28
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_FORCE [27:27] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_MASK 0x08000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_SHIFT 27
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_ENABLE [26:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_ENABLE_MASK 0x04000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_ENABLE_SHIFT 26
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_LENGTH [25:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_LENGTH_MASK 0x03c00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_LENGTH_SHIFT 22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_LENGTH_DEFAULT 0x0000000c

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT1_DELAY [21:16] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_DELAY_MASK 0x003f0000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_DELAY_SHIFT 16
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT1_DELAY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_reserved1_SHIFT 13

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_FORCE_VALUE [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_MASK 0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_SHIFT 12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_FORCE [11:11] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_MASK 0x00000800
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_SHIFT 11
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_FORCE_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_ENABLE [10:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_ENABLE_MASK 0x00000400
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_ENABLE_SHIFT 10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_LENGTH [09:06] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_LENGTH_MASK 0x000003c0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_LENGTH_SHIFT 6
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_LENGTH_DEFAULT 0x0000000c

/* DDR34_PHY_CONTROL_REGS_0 :: WRITE_ODT_CNTRL :: ODT0_DELAY [05:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_DELAY_MASK 0x0000003f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_DELAY_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_WRITE_ODT_CNTRL_ODT0_DELAY_DEFAULT 0x00000000

/***************************************************************************
 *ABI_PAR_CNTRL - ABI and PAR Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: reserved0 [31:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_MASK 0xffffff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_reserved0_SHIFT 8

/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_ERROR [07:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ERROR_MASK 0x000000f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ERROR_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *ZQ_CAL - ZQ Calibration Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: reserved0 [31:31] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_MASK        0x80000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_reserved0_SHIFT       31

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_LSTRIM [30:27] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_LSTRIM_MASK     0x78000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_LSTRIM_SHIFT    27
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_LSTRIM_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_ITRIM [26:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_ITRIM_MASK      0x07000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_ITRIM_SHIFT     24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_ITRIM_DEFAULT   0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_TX_SLEW [23:22] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_SLEW_MASK       0x00c00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_SLEW_SHIFT      22
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_SLEW_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_STATUS [21:21] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_MASK        0x00200000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_SHIFT       21
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_STATUS_DEFAULT     0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RXENB [20:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_MASK         0x00100000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RXENB_SHIFT        20

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_IDDQ [19:19] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_MASK          0x00080000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_SHIFT         19
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_IDDQ_DEFAULT       0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_N [18:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_MASK       0x0007c000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_SHIFT      14
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_N_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_DRIVE_P [13:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_MASK       0x00003e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_SHIFT      9
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_DRIVE_P_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_TX_MODE [08:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_MASK       0x000001f8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_SHIFT      3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_TX_MODE_DEFAULT    0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL :: ZQ_RX_MODE [02:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_MASK       0x00000007
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_SHIFT      0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL_ZQ_RX_MODE_DEFAULT    0x00000000

/***************************************************************************
 *ZQ_CAL2 - ZQ Calibration Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: reserved0 [31:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_reserved0_MASK       0xffffc000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_reserved0_SHIFT      14

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_NSETTING [13:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_NSETTING_MASK     0x00003e00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_NSETTING_SHIFT    9
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_NSETTING_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_PSETTING [08:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_PSETTING_MASK     0x000001f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_PSETTING_SHIFT    4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_PSETTING_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_OP_COMPLETE_N [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_OP_COMPLETE_P [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_MASK 0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_START_N [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_N_MASK  0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_N_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_N_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: ZQ_CAL2 :: ZQ_CAL_START_P [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_P_MASK  0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_P_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_ZQ_CAL2_ZQ_CAL_START_P_DEFAULT 0x00000000

/***************************************************************************
 *COMR_CAL - COMR Calibration Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: reserved0 [31:14] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved0_MASK      0xffffc000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved0_SHIFT     14

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_DIN [13:13] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_DIN_MASK    0x00002000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_DIN_SHIFT   13

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_READY [12:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_READY_MASK  0x00001000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_READY_SHIFT 12

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RXENB [11:11] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RXENB_MASK     0x00000800
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RXENB_SHIFT    11
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RXENB_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: reserved1 [10:09] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved1_MASK      0x00000600
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_reserved1_SHIFT     9

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_MODE [08:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_MODE_MASK   0x00000100
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_MODE_SHIFT  8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_MODE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_LSTRIM [07:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_LSTRIM_MASK 0x000000f0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_LSTRIM_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_RX_ITRIM [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_ITRIM_MASK  0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_ITRIM_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_RX_ITRIM_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: COMR_CAL :: COMR_IDDQ [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_IDDQ_MASK      0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_IDDQ_SHIFT     0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_COMR_CAL_COMR_IDDQ_DEFAULT   0x00000000

/***************************************************************************
 *RO_PROC_MON_CTL - Ring-Osc control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: reserved0 [31:27] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_reserved0_MASK 0xf8000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_reserved0_SHIFT 27

/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: BUSY [26:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_BUSY_MASK    0x04000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_BUSY_SHIFT   26
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: TRIGGER [25:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_TRIGGER_MASK 0x02000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_TRIGGER_SHIFT 25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_TRIGGER_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: RESET [24:24] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_RESET_MASK   0x01000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_RESET_SHIFT  24
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_RESET_DEFAULT 0x00000001

/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: SEL [23:12] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_SEL_MASK     0x00fff000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_SEL_SHIFT    12
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_SEL_DEFAULT  0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_CTL :: EN [11:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_EN_MASK      0x00000fff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_EN_SHIFT     0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_CTL_EN_DEFAULT   0x00000000

/***************************************************************************
 *RO_PROC_MON_STATUS - Ring-Osc count register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_STATUS :: CLK_COUNT [31:08] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_CLK_COUNT_MASK 0xffffff00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_CLK_COUNT_SHIFT 8
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_CLK_COUNT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: RO_PROC_MON_STATUS :: RO_COUNT [07:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_RO_COUNT_MASK 0x000000ff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_RO_COUNT_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_RO_PROC_MON_STATUS_RO_COUNT_DEFAULT 0x00000000

/***************************************************************************
 *CK_DRIVE_PAD_CTL - Drive strength control register for CK_P and CK_N
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_reserved0_SHIFT 30

/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x00000010

/* DDR34_PHY_CONTROL_REGS_0 :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x00000010

/***************************************************************************
 *LDO_COMP_CONTROL - LDO Comparator Control register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_reserved0_MASK 0xffffffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_reserved0_SHIFT 5

/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: AUX_GT_INT [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_AUX_GT_INT_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_AUX_GT_INT_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_AUX_GT_INT_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: TESTOUT_MUX_CTL [03:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TESTOUT_MUX_CTL_MASK 0x0000000e
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TESTOUT_MUX_CTL_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: LDO_COMP_CONTROL :: TEST [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TEST_MASK   0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TEST_SHIFT  0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_LDO_COMP_CONTROL_TEST_DEFAULT 0x00000000

/***************************************************************************
 *BYTE_LANE_ALIGN_MASKS - Byte-lane alignment mask register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: reserved0 [31:26] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_reserved0_MASK 0xfc000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_reserved0_SHIFT 26

/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: MASK_ENABLE [25:25] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_MASK 0x02000000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_SHIFT 25
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL4_MASK [24:20] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL4_MASK_MASK 0x01f00000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL4_MASK_SHIFT 20
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL4_MASK_DEFAULT 0x00000010

/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL3_MASK [19:15] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL3_MASK_MASK 0x000f8000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL3_MASK_SHIFT 15
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL3_MASK_DEFAULT 0x0000000f

/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL2_MASK [14:10] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL2_MASK_MASK 0x00007c00
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL2_MASK_SHIFT 10
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL2_MASK_DEFAULT 0x0000000f

/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL1_MASK [09:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL1_MASK_MASK 0x000003e0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL1_MASK_SHIFT 5
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL1_MASK_DEFAULT 0x0000000f

/* DDR34_PHY_CONTROL_REGS_0 :: BYTE_LANE_ALIGN_MASKS :: BL0_MASK [04:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL0_MASK_MASK 0x0000001f
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL0_MASK_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_BYTE_LANE_ALIGN_MASKS_BL0_MASK_DEFAULT 0x0000000f

/***************************************************************************
 *CLOCK_IDLE - Clock Idle Register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_reserved0_MASK    0xffffffe0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_reserved0_SHIFT   5

/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: BIT_CLOCK_CS [04:04] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_CS_MASK 0x00000010
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_CS_SHIFT 4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_CS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: BIT_CLOCK_LS [03:03] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_LS_MASK 0x00000008
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_LS_SHIFT 3
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_LS_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_TO_MC_CLOCK_MASK  0x00000004
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000

/* DDR34_PHY_CONTROL_REGS_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_MASK    0x00000001
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_SHIFT   0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *AC_SPARE_REG - Address and Control Spare register
 ***************************************************************************/
/* DDR34_PHY_CONTROL_REGS_0 :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_SHIFT 0
#define BCHP_DDR34_PHY_CONTROL_REGS_0_AC_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000

#endif /* #ifndef BCHP_DDR34_PHY_CONTROL_REGS_0_H__ */

/* End of File */