/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Tue Dec  2 03:18:44 2014
 *                 Full Compile MD5 Checksum 3461841ff250f7118305e1f1650424cf
 *                   (minus title and desc)  
 *                 MD5 Checksum              92044aba65695bbffdeefc8d096b8587
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008008
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_H__

/***************************************************************************
 *DDR34_PHY_BYTE_LANE_2_0 - DDR34 Byte Lane #2 control registers
 ***************************************************************************/
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS 0x00506800 /* Write channel DQS VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0 0x00506804 /* Write channel DQ0 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1 0x00506808 /* Write channel DQ1 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2 0x0050680c /* Write channel DQ2 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3 0x00506810 /* Write channel DQ3 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4 0x00506814 /* Write channel DQ4 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5 0x00506818 /* Write channel DQ5 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6 0x0050681c /* Write channel DQ6 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7 0x00506820 /* Write channel DQ7 VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM 0x00506824 /* Write channel DM VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC 0x00506828 /* Write channel EDC VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP 0x0050682c /* Read channel DQSP VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN 0x00506830 /* Read channel DQSP VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P 0x00506834 /* Read channel DQ0-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N 0x00506838 /* Read channel DQ0-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P 0x0050683c /* Read channel DQ1-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N 0x00506840 /* Read channel DQ1-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P 0x00506844 /* Read channel DQ2-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N 0x00506848 /* Read channel DQ2-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P 0x0050684c /* Read channel DQ3-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N 0x00506850 /* Read channel DQ3-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P 0x00506854 /* Read channel DQ4-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N 0x00506858 /* Read channel DQ4-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P 0x0050685c /* Read channel DQ5-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N 0x00506860 /* Read channel DQ5-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P 0x00506864 /* Read channel DQ6-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N 0x00506868 /* Read channel DQ6-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P 0x0050686c /* Read channel DQ7-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N 0x00506870 /* Read channel DQ7-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP 0x00506874 /* Read channel DM-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN 0x00506878 /* Read channel DM-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP 0x0050687c /* Read channel EDC-P VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN 0x00506880 /* Read channel EDC-N VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0 0x00506884 /* Read channel CS_N[0] read enable VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1 0x00506888 /* Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active) */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC 0x0050688c /* Read channel GDDR5 CRC read enable VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL 0x00506890 /* DDR interface signal Write Leveling CLK VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL 0x00506894 /* DDR interface signal Write Leveling Capture Enable VDL control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC 0x00506898 /* Read enable bit-clock cycle delay control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC 0x0050689c /* Write leveling bit-clock cycle delay control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL 0x005068a0 /* Read channel datapath control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR 0x005068a4 /* Read fifo addresss pointer register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA 0x005068a8 /* Read fifo data register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI 0x005068ac /* Read fifo dm/dbi register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS 0x005068b0 /* Read fifo status register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR 0x005068b4 /* Read fifo status clear register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL 0x005068b8 /* Idle mode SSTL pad control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL 0x005068bc /* DQ, DM pad drive characteristics control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL 0x005068c0 /* DQS pad P rail  drive characteristics control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL 0x005068c4 /* DQS pad N rail  drive characteristics control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL 0x005068c8 /* EDC pad drive characteristics control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL 0x005068cc /* RD_EN, EDC_RD_EN read enable pad drive characteristics control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL 0x005068d0 /* pad rx and tx characteristics control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM  0x005068d4 /* Receiver trim for DQ */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM 0x005068d8 /* Receiver trim for miscellaneous pins */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM 0x005068dc /* Rreceiver trim for DQS */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE 0x005068e0 /* Write cycle preamble control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL 0x005068e4 /* Read channel ODT control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG  0x005068e8 /* LDO Configuration register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL 0x005068ec /* GDDR5M EDC digital phase detector control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS 0x005068f0 /* GDDR5M EDC digital phase detector status register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL 0x005068f4 /* GDDR5M EDC digital phase detector output signal control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS 0x005068f8 /* GDDR5M EDC digital phase detector output signal status register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR 0x005068fc /* GDDR5M EDC digital phase detector output signal status clear register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL 0x00506900 /* GDDR5M EDC signal path CRC control register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS 0x00506904 /* GDDR5M EDC signal path CRC status register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT 0x00506908 /* GDDR5M EDC signal path CRC counter register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR 0x0050690c /* GDDR5M EDC signal path CRC counter register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE 0x00506910 /* Clock Enable Register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE  0x00506914 /* Clock Idle Register */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG 0x00506918 /* Byte-Lane Spare register */

/***************************************************************************
 *VDL_CONTROL_WR_DQS - Write channel DQS VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_DM - Write channel DM VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active)
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CONTROL_RD_EN_CRC - Read channel GDDR5 CRC read enable VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_BUSY_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_BUSY_SHIFT 31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_FORCE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_FORCE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: reserved2 [11:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved2_MASK 0x00000f00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_reserved2_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CRC :: VDL_STEP [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CRC_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_SHIFT    31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_SHIFT   16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_MASK     0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_SHIFT    31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_BUSY_DEFAULT  0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_MASK    0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_SHIFT   16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved1_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_MASK   0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT  12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000

/***************************************************************************
 *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_SHIFT      31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_SHIFT     16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved1 [15:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_MASK  0x0000c000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_SHIFT 14

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CRC_CYCLES [13:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CRC_CYCLES_MASK 0x00003c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CRC_CYCLES_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CRC_CYCLES_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved2 [09:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved2_MASK  0x00000200
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_ENABLE_CS1_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000

/***************************************************************************
 *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000ff00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_DQ_CYCLES_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved2_MASK 0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved2_SHIFT 3

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000

/***************************************************************************
 *READ_CONTROL - Read channel datapath control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved0 [31:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_MASK   0xffffffe0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_SHIFT  5

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: MODE [04:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_MASK        0x00000010
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_SHIFT       4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_DEFAULT     0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_EN_MODE [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_EN_MODE_MASK  0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_EN_MODE_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_EN_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007

/***************************************************************************
 *READ_FIFO_ADDR - Read fifo addresss pointer register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_SHIFT 3

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_MASK      0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_SHIFT     0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000

/***************************************************************************
 *READ_FIFO_DATA - Read fifo data register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DATA :: DATA [31:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_MASK      0xffffffff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_SHIFT     0

/***************************************************************************
 *READ_FIFO_DM_DBI - Read fifo dm/dbi register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0

/***************************************************************************
 *READ_FIFO_STATUS - Read fifo status register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_SHIFT 2

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000

/***************************************************************************
 *READ_FIFO_CLEAR - Read fifo status clear register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_SHIFT 1

/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_SHIFT   0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000

/***************************************************************************
 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_SHIFT   31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000003

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000003

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_SHIFT  3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000

/***************************************************************************
 *DRIVE_PAD_CTL - DQ, DM pad drive characteristics control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_MASK  0xc0000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_SHIFT 30

/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000

/***************************************************************************
 *DQSP_DRIVE_PAD_CTL - DQS pad P rail  drive characteristics control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_reserved0_SHIFT 30

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000

/***************************************************************************
 *DQSN_DRIVE_PAD_CTL - DQS pad N rail  drive characteristics control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_reserved0_SHIFT 30

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000

/***************************************************************************
 *EDC_DRIVE_PAD_CTL - EDC pad drive characteristics control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: reserved0 [31:30] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_reserved0_SHIFT 30

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x00000000

/***************************************************************************
 *RD_EN_DRIVE_PAD_CTL - RD_EN, EDC_RD_EN read enable pad drive characteristics control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x00000000

/***************************************************************************
 *STATIC_PAD_CTL - pad rx and tx characteristics control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved0 [31:25] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_MASK 0xfe000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_SHIFT 25

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_SLEW [24:23] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_SLEW_MASK   0x01800000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_SLEW_SHIFT  23
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_SLEW_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_MODE [22:22] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_MASK  0x00400000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 22
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved1 [21:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_MASK 0x00300000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_SHIFT 20

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: EDC_MODE [19:18] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_MASK  0x000c0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 18
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved2 [17:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_MASK 0x00020000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DM_MODE [14:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_MASK   0x00004000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_SHIFT  14
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved3 [13:13] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_MASK 0x00002000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_SHIFT 13

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_PAUSE [12:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_MASK 0x00001000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_PAUSE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved_for_padding4 [11:11] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved_for_padding4_MASK 0x00000800
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved_for_padding4_SHIFT 11

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [10:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000400
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_MODE [09:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_MASK   0x000003f0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_SHIFT  4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved5 [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_MASK 0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved5_SHIFT 3

/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_SHIFT  0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000

/***************************************************************************
 *DQ_RX_TRIM - Receiver trim for DQ
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_reserved0_MASK     0xffe00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_reserved0_SHIFT    21

/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: LSTRIM [20:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_LSTRIM_MASK        0x001e0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_LSTRIM_SHIFT       17
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_LSTRIM_DEFAULT     0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: ITRIM [16:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_ITRIM_MASK         0x0001c000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_ITRIM_SHIFT        14
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_ITRIM_DEFAULT      0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: IDLE_LSTRIM [13:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_LSTRIM_MASK   0x00003c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_LSTRIM_SHIFT  10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: IDLE_ITRIM [09:07] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_ITRIM_MASK    0x00000380
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_ITRIM_SHIFT   7
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: TERM_LSTRIM [06:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_LSTRIM_MASK   0x00000078
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_LSTRIM_SHIFT  3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQ_RX_TRIM :: TERM_ITRIM [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_ITRIM_MASK    0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_ITRIM_SHIFT   0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQ_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000

/***************************************************************************
 *MISC_RX_TRIM - Receiver trim for miscellaneous pins
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_reserved0_MASK   0xffe00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_reserved0_SHIFT  21

/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: LSTRIM [20:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_LSTRIM_MASK      0x001e0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_LSTRIM_SHIFT     17
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_LSTRIM_DEFAULT   0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: ITRIM [16:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_ITRIM_MASK       0x0001c000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_ITRIM_SHIFT      14
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_ITRIM_DEFAULT    0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: IDLE_LSTRIM [13:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_LSTRIM_MASK 0x00003c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_LSTRIM_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: IDLE_ITRIM [09:07] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_ITRIM_MASK  0x00000380
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_ITRIM_SHIFT 7
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: TERM_LSTRIM [06:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_LSTRIM_MASK 0x00000078
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_LSTRIM_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: MISC_RX_TRIM :: TERM_ITRIM [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_ITRIM_MASK  0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_ITRIM_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_MISC_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000

/***************************************************************************
 *DQS_RX_TRIM - Rreceiver trim for DQS
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_reserved0_MASK    0xffe00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_reserved0_SHIFT   21

/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: LSTRIM [20:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_LSTRIM_MASK       0x001e0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_LSTRIM_SHIFT      17
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_LSTRIM_DEFAULT    0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: ITRIM [16:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_ITRIM_MASK        0x0001c000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_ITRIM_SHIFT       14
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_ITRIM_DEFAULT     0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: IDLE_LSTRIM [13:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_LSTRIM_MASK  0x00003c00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_LSTRIM_SHIFT 10
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: IDLE_ITRIM [09:07] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_ITRIM_MASK   0x00000380
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_ITRIM_SHIFT  7
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_IDLE_ITRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: TERM_LSTRIM [06:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_LSTRIM_MASK  0x00000078
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_LSTRIM_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_LSTRIM_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: DQS_RX_TRIM :: TERM_ITRIM [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_ITRIM_MASK   0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_ITRIM_SHIFT  0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DQS_RX_TRIM_TERM_ITRIM_DEFAULT 0x00000000

/***************************************************************************
 *WR_PREAMBLE_MODE - Write cycle preamble control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffe00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_SHIFT 21

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_DEFAULT 0x00000003

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS [08:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_MASK     0x000001e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_SHIFT    5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000a

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002

/***************************************************************************
 *ODT_CONTROL - Read channel ODT control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31

/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved1 [30:10] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_MASK    0x7ffffc00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved1_SHIFT   10

/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_MASK   0x00000200
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_SHIFT  9
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_MASK    0x000001c0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_SHIFT   6
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003

/***************************************************************************
 *LDO_CONFIG - LDO Configuration register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: reserved0 [31:06] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_reserved0_MASK     0xffffffc0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_reserved0_SHIFT    6

/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_PWRDOWN [05:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_PWRDOWN_MASK 0x00000020
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_PWRDOWN_SHIFT 5
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_PWRDOWN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_REF_SEL [04:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_SEL_MASK 0x00000010
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_SEL_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_SEL_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_REF_CTRL [03:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_CTRL_MASK 0x0000000c
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_CTRL_SHIFT 2
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: LDO_CONFIG :: CK_LDO_BIAS [01:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_BIAS_MASK   0x00000003
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_BIAS_SHIFT  0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_LDO_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000000

/***************************************************************************
 *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved0 [31:22] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_MASK 0xffc00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_SHIFT 22

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [21:21] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00200000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 21
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [20:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00100000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 20
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved1 [19:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved1_MASK 0x000f0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved1_SHIFT 16

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: TARGET_CS_N [15:15] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_TARGET_CS_N_MASK 0x00008000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_TARGET_CS_N_SHIFT 15
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_TARGET_CS_N_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE_MODE [14:14] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MODE_MASK 0x00004000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MODE_SHIFT 14
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SAMPLE_MODE [13:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SAMPLE_MODE_MASK 0x00003000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SAMPLE_MODE_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SAMPLE_MODE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved2 [11:09] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved2_MASK 0x00000e00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved2_SHIFT 9

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MIN_LOW_SAMPLES [08:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_MASK 0x000001f0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MIN_LOW_SAMPLES_DEFAULT 0x00000008

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_SHIFT  2
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_MASK     0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_SHIFT    0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000

/***************************************************************************
 *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved0 [31:29] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_MASK 0xe0000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_SHIFT 29

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [28:28] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x10000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 28
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [27:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x0ff00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 20
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved1 [19:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_MASK 0x000e0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [15:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x0000ff00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 8
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved2 [07:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved2_MASK 0x000000e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved2_SHIFT 5

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_ERROR [04:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_ERROR_MASK 0x00000010
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_ERROR_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_ERROR_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 3
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_LOCK [02:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_LOCK_MASK 0x00000004
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_LOCK_SHIFT 2
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_LOCK_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000

/***************************************************************************
 *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000

/***************************************************************************
 *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000

/***************************************************************************
 *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_SHIFT    31
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_SHIFT 17

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_SHIFT   16
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_SHIFT 11

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_SHIFT   8
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_SHIFT 6

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_SHIFT   4
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved3 [03:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_MASK 0x0000000c
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_SHIFT 2

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000

/***************************************************************************
 *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MISCOMPARE_EXP_CRC [31:24] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_MASK 0xff000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_EXP_CRC_SHIFT 24

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MISCOMPARE_CRC [23:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_CRC_MASK 0x00ff0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_CRC_SHIFT 16

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MOST_RECENT_CRC [15:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MOST_RECENT_CRC_MASK 0x0000ff00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MOST_RECENT_CRC_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: reserved0 [07:05] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_MASK 0x000000e0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_SHIFT 5

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: MISCOMPARE_TYPE [04:04] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_MASK 0x00000010
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_MISCOMPARE_TYPE_SHIFT 4

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_SHIFT  3

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_SHIFT  2

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_SHIFT  1

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_SHIFT  0

/***************************************************************************
 *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_FAIL_COUNT [31:24] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_FAIL_COUNT_MASK 0xff000000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_FAIL_COUNT_SHIFT 24

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_PASS_COUNT [23:16] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_PASS_COUNT_MASK 0x00ff0000
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_PASS_COUNT_SHIFT 16

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_FAIL_COUNT [15:08] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_FAIL_COUNT_MASK 0x0000ff00
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_FAIL_COUNT_SHIFT 8

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_PASS_COUNT [07:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_PASS_COUNT_MASK 0x000000ff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_PASS_COUNT_SHIFT 0

/***************************************************************************
 *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1

/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000

/***************************************************************************
 *CLOCK_ENABLE - Clock Enable Register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_reserved0_SHIFT  3

/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_TO_MC_CLOCK_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_FROM_MC_CLOCK_DEFAULT 0x00000001

/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_BIT_CLOCK_MASK   0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_BIT_CLOCK_SHIFT  0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_ENABLE_BIT_CLOCK_DEFAULT 0x00000001

/***************************************************************************
 *CLOCK_IDLE - Clock Idle Register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: reserved0 [31:03] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_reserved0_MASK     0xfffffff8
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_reserved0_SHIFT    3

/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_TO_MC_CLOCK_MASK   0x00000004
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT  2
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_TO_MC_CLOCK_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_FROM_MC_CLOCK_DEFAULT 0x00000000

/* DDR34_PHY_BYTE_LANE_2_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_BIT_CLOCK_MASK     0x00000001
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_BIT_CLOCK_SHIFT    0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_CLOCK_IDLE_BIT_CLOCK_DEFAULT  0x00000000

/***************************************************************************
 *BL_SPARE_REG - Byte-Lane Spare register
 ***************************************************************************/
/* DDR34_PHY_BYTE_LANE_2_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000

#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__ */

/* End of File */