| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Sat Sep 13 03:11:32 2014 |
| * Full Compile MD5 Checksum 81d1dc071f09e844b7694a9d7010032b |
| * (minus title and desc) |
| * MD5 Checksum 8011b86e52a731b78eada82a643ab85a |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_AON_PIN_CTRL_H__ |
| #define BCHP_AON_PIN_CTRL_H__ |
| |
| /*************************************************************************** |
| *AON_PIN_CTRL - AON Pinmux Control Registers |
| ***************************************************************************/ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0 0x00410700 /* Pinmux control register 0 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1 0x00410704 /* Pinmux control register 1 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2 0x00410708 /* Pinmux control register 2 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3 0x0041070c /* Pinmux control register 3 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0 0x00410710 /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1 0x00410714 /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0 0x00410718 /* Bypass clock unselect register 0 */ |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [31:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK 0xf0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_KD_3 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LD_11 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_I2S_LR0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MTSIF1_DATA6 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_VO0_656_7 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SC1_AUX1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SD_CARD0_DAT3 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_TP_OUT_16 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_PM_AON_GPIO_06 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [27:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK 0x0f000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_KD_2 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD_10 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF1_DATA7 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_VO0_656_6 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_PRES 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SD_CARD0_DAT2 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_OUT_19 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [23:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK 0x00f00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_KD_1 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD_9 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MTSIF_ATS_RST 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_VO0_656_5 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_IO 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SD_CARD0_DAT1 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_OUT_18 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [19:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK 0x000f0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_0 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_LD_8 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_RSVD 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MTSIF1_DATA5 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_VO0_656_1 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SC1_AUX2 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SD_CARD0_DAT0 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_18 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_ENET0_LINK 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AUD_FS_CLK1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_VEC_VSYNC 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TSIO_VCTRL 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_ENET0_ACTIVITY 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_IR_OUT 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_LR0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TP_IN_15 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_LINK 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SPI_M_SS1B 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_ACTIVITY 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_15 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_IR_INT 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PWM1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SPI_M_SS2B 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TSIO_VCTRL 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_OUT 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_I2S_DATA0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_IN_16 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi0_tx_cec [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi0_tx_cec_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi0_tx_cec_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi0_tx_cec_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi0_tx_cec_AON_HDMI0_TX_CEC 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi0_tx_cec_TP_IN_21 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [31:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK 0xf0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_2 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_RTS_1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SPI_S_SS0B 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MTSIF1_SYNC 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PWM3 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PKT_SYNC1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SD_CARD0_PRES 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_TP_OUT_26 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_PM_AON_GPIO_14 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [27:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK 0x0f000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_1 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_TXD_1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ENET0_LINK 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF_ATS_INC 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_RSVD 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SC1_VPP 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ALT_TP_OUT_00 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [23:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK 0x00f00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_0 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_RXD_1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_IN 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF1_DATA0 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_IR_IN1 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT_DATA1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SD_CARD0_CLK_IN 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_ALT_TP_IN_00 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [19:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK 0x000f0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LS_4 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_CTS_0 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_IN 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MTSIF1_CLK 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_VO0_656_4 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_PKT_CLK1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SD_CARD0_CMD 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MPM_UART_RXD 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_IN_24 9 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_PM_AON_GPIO_11 10 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LS_3 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS_0 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_15 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_RMX_VALID0_ALT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_VO0_656_3 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_IR_OUT 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_CLK0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MPM_UART_TXD 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_24 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LS_2 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_14 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_SS2B 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_RMX_SYNC0_ALT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_VO0_656_2 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SD_CARD0_PWR0 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_22 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_1 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD_13 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_RMX_DATA0_ALT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_VO0_656_0 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_CLK 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SD_CARD0_CLK 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_OUT_22 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LS_0 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD_12 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_RSVD 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_RMX_CLK0_ALT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_VO0_656_CLK 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_VCC 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SD_CARD0_LED 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MHL_POWERUPB 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_OUT_21 9 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [31:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK 0xf0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_HDMI_TX0_BSC_SDA 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [27:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK 0x0f000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_HDMI_TX0_BSC_SCL 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [23:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK 0x00f00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_OUT 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_ENET0_LINK 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_FP_4SEC_RESETB 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF1_DATA4 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_IR_IN1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RMX_PAUSE0_ALT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_19 9 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 10 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [19:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK 0x000f0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_LD_7 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_UART_RTS_2 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_SS0B 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AUD_FS_CLK1 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_OUT 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_RSVD_1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AUD_FS_CLK0 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MPM_SF_CSB 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_28 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_LD_6 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_UART_CTS_2 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_MISO 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF1_DATA3 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_ENET0_ACTIVITY 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT_SYNC0 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_I2S_LR0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MPM_SF_MISO 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_OUT_28 9 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 10 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_LD_5 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_UART_TXD_2 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF1_DATA2 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_RSVD 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT_DATA0 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_I2S_DATA0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MPM_SF_MOSI 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_ALT_TP_OUT_01 9 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 10 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_4 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_UART_RXD_2 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF1_VALID 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ENET0_LINK 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT_CLK0 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_I2S_CLK0_OUT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MPM_SF_SCK 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_ALT_TP_IN_01 9 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 10 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LD_3 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_UART_CTS_1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_I2S_LR0_IN 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF1_DATA1 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PWM2 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_S_MISO 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SD_CARD0_WPROT 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_26 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 9 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK 0xffff0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT 16 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_07 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_AON_SGPIO_07 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_07_BSC_M3_SDA 1 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_06 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_AON_SGPIO_06 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_06_BSC_M3_SCL 1 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_05 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_SGPIO_05 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_M2_SDA 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_HDMI_RX_BSC_SDA 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_S1_SDA 3 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_04 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_SGPIO_04 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_M2_SCL 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_HDMI_RX_BSC_SCL 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_S1_SCL 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_11_pad_ctrl [29:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_MASK 0x30000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [27:26] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x0c000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 26 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_09_pad_ctrl [25:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_MASK 0x03000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [23:22] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 22 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [21:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x00300000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [19:18] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 18 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [17:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00030000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [15:14] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 14 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [13:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00003000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [11:10] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00000c00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 10 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [09:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00000300 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved2 [07:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_MASK 0x000000ff |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:18] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3ffc0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 18 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [17:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00030000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [15:14] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 14 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [13:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00003000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [11:10] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 10 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [09:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00000300 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [07:06] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [05:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000030 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [03:02] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x0000000c |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [01:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x00000003 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:06] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffffffc0 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 6 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_17 [05:05] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_17_MASK 0x00000020 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_17_SHIFT 5 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_17_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_16 [04:04] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_16_MASK 0x00000010 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_16_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_16_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_13 [03:03] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_13_MASK 0x00000008 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_13_SHIFT 3 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_13_DEFAULT 0x00000001 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_12 [02:02] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_12_MASK 0x00000004 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_12_SHIFT 2 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_12_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [01:01] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000002 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 1 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_s3_standbyb [00:00] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_s3_standbyb_MASK 0x00000001 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_s3_standbyb_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_s3_standbyb_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */ |
| |
| /* End of File */ |
