/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Fri Oct 25 17:33:13 2013
 *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
 *                   (minus title and desc)  
 *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008005
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_SWITCH_INTRL2_0_H__
#define BCHP_SWITCH_INTRL2_0_H__

/***************************************************************************
 *SWITCH_INTRL2_0
 ***************************************************************************/
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS          0x04e40340 /* CPU interrupt Status Register */
#define BCHP_SWITCH_INTRL2_0_CPU_SET             0x04e40344 /* CPU interrupt Set Register */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR           0x04e40348 /* CPU interrupt Clear Register */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS     0x04e4034c /* CPU interrupt Mask Status Register */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET        0x04e40350 /* CPU interrupt Mask Set Register */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR      0x04e40354 /* CPU interrupt Mask Clear Register */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS          0x04e40358 /* PCI interrupt Status Register */
#define BCHP_SWITCH_INTRL2_0_PCI_SET             0x04e4035c /* PCI interrupt Set Register */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR           0x04e40360 /* PCI interrupt Clear Register */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS     0x04e40364 /* PCI interrupt Mask Status Register */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET        0x04e40368 /* PCI interrupt Mask Set Register */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR      0x04e4036c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: CPU_STATUS :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_reserved0_MASK             0xfffc0000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_reserved0_SHIFT            18

/* SWITCH_INTRL2_0 :: CPU_STATUS :: TCAM_soft_err_intr [17:17] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_TCAM_soft_err_intr_MASK    0x00020000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_TCAM_soft_err_intr_SHIFT   17
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_TCAM_soft_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: failover_off_intr [16:16] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_MASK     0x00010000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_SHIFT    16
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: failover_on_intr [15:15] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_MASK      0x00008000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_SHIFT     15
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: ubus_err_intr [14:14] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_MASK         0x00004000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_SHIFT        14
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: gisb_err_intr [13:13] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_MASK         0x00002000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_SHIFT        13
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: mdio_done_intr [12:12] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_MASK        0x00001000
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_SHIFT       12
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: mdio_err_up_intr [11:11] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_MASK      0x00000800
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_SHIFT     11
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: 1588_intr [10:10] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_MASK             0x00000400
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_SHIFT            10
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p7_cpu_wake_timer_intr [09:09] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p8_cpu_wake_timer_intr [08:08] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p5_cpu_wake_timer_intr [07:07] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: eee_lpi_intr [06:06] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_MASK          0x00000040
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_SHIFT         6
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: memory_double_err_intr [05:05] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_MASK          0x00000010
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_SHIFT         4
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_MASK    0x00000008
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_SHIFT   3
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_MASK     0x00000004
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_SHIFT    2
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_MASK     0x00000002
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_SHIFT    1
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_MASK       0x00000001
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_SHIFT      0
#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_DEFAULT    0x00000000

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: CPU_SET :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_reserved0_MASK                0xfffc0000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_reserved0_SHIFT               18

/* SWITCH_INTRL2_0 :: CPU_SET :: TCAM_soft_err_intr [17:17] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_TCAM_soft_err_intr_MASK       0x00020000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_TCAM_soft_err_intr_SHIFT      17
#define BCHP_SWITCH_INTRL2_0_CPU_SET_TCAM_soft_err_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: failover_off_intr [16:16] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_MASK        0x00010000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_SHIFT       16
#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: failover_on_intr [15:15] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_MASK         0x00008000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_SHIFT        15
#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: ubus_err_intr [14:14] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_MASK            0x00004000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_SHIFT           14
#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_DEFAULT         0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: gisb_err_intr [13:13] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_MASK            0x00002000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_SHIFT           13
#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_DEFAULT         0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: mdio_done_intr [12:12] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_MASK           0x00001000
#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_SHIFT          12
#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: mdio_err_up_intr [11:11] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_MASK         0x00000800
#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_SHIFT        11
#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: 1588_intr [10:10] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_MASK                0x00000400
#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_SHIFT               10
#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_DEFAULT             0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p7_cpu_wake_timer_intr [09:09] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_MASK   0x00000200
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_SHIFT  9
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p8_cpu_wake_timer_intr [08:08] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_MASK   0x00000100
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_SHIFT  8
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p5_cpu_wake_timer_intr [07:07] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_MASK   0x00000080
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_SHIFT  7
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: eee_lpi_intr [06:06] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_MASK             0x00000040
#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_SHIFT            6
#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: memory_double_err_intr [05:05] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_MASK   0x00000020
#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_SHIFT  5
#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p0_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_MASK             0x00000010
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_SHIFT            4
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p0_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_MASK       0x00000008
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_SHIFT      3
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p0_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_MASK        0x00000004
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_SHIFT       2
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p0_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_MASK        0x00000002
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_SHIFT       1
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: CPU_SET :: p0_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_MASK          0x00000001
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_SHIFT         0
#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_DEFAULT       0x00000000

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: CPU_CLEAR :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_reserved0_MASK              0xfffc0000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_reserved0_SHIFT             18

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: TCAM_soft_err_intr [17:17] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_TCAM_soft_err_intr_MASK     0x00020000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_TCAM_soft_err_intr_SHIFT    17
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_TCAM_soft_err_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: failover_off_intr [16:16] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_MASK      0x00010000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_SHIFT     16
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: failover_on_intr [15:15] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_MASK       0x00008000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_SHIFT      15
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: ubus_err_intr [14:14] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_MASK          0x00004000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_SHIFT         14
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: gisb_err_intr [13:13] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_MASK          0x00002000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_SHIFT         13
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: mdio_done_intr [12:12] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_MASK         0x00001000
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_SHIFT        12
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: mdio_err_up_intr [11:11] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_MASK       0x00000800
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_SHIFT      11
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: 1588_intr [10:10] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_MASK              0x00000400
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_SHIFT             10
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_DEFAULT           0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p7_cpu_wake_timer_intr [09:09] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p8_cpu_wake_timer_intr [08:08] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p5_cpu_wake_timer_intr [07:07] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: eee_lpi_intr [06:06] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_MASK           0x00000040
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_SHIFT          6
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: memory_double_err_intr [05:05] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_MASK           0x00000010
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_SHIFT          4
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_MASK     0x00000008
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_SHIFT    3
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_MASK      0x00000004
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_SHIFT     2
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_MASK      0x00000002
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_SHIFT     1
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_MASK        0x00000001
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_SHIFT       0
#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_DEFAULT     0x00000000

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_reserved0_MASK        0xfffc0000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_reserved0_SHIFT       18

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: TCAM_soft_err_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_TCAM_soft_err_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_TCAM_soft_err_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_TCAM_soft_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: failover_off_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: failover_on_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: ubus_err_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: gisb_err_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: mdio_done_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: mdio_err_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: 1588_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_MASK   0x00000400
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_SHIFT  10
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p7_cpu_wake_timer_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p8_cpu_wake_timer_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p5_cpu_wake_timer_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: eee_lpi_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: memory_double_err_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_reserved0_MASK           0xfffc0000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_reserved0_SHIFT          18

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: TCAM_soft_err_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_TCAM_soft_err_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_TCAM_soft_err_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_TCAM_soft_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: failover_off_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: failover_on_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: ubus_err_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_MASK  0x00004000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: gisb_err_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_MASK  0x00002000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: mdio_done_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: mdio_err_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_MASK  0x00000800
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: 1588_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_MASK      0x00000400
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_SHIFT     10
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_DEFAULT   0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p7_cpu_wake_timer_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p8_cpu_wake_timer_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p5_cpu_wake_timer_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: eee_lpi_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_MASK   0x00000040
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_SHIFT  6
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: memory_double_err_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_MASK   0x00000010
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_SHIFT  4
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_reserved0_MASK         0xfffc0000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_reserved0_SHIFT        18

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: TCAM_soft_err_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_TCAM_soft_err_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_TCAM_soft_err_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_TCAM_soft_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: failover_off_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: failover_on_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: ubus_err_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: gisb_err_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: mdio_done_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: mdio_err_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: 1588_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_MASK    0x00000400
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_SHIFT   10
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p7_cpu_wake_timer_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p8_cpu_wake_timer_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p5_cpu_wake_timer_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: eee_lpi_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: memory_double_err_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: PCI_STATUS :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_reserved0_MASK             0xfffc0000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_reserved0_SHIFT            18

/* SWITCH_INTRL2_0 :: PCI_STATUS :: TCAM_soft_err_intr [17:17] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_TCAM_soft_err_intr_MASK    0x00020000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_TCAM_soft_err_intr_SHIFT   17
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_TCAM_soft_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: failover_off_intr [16:16] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_MASK     0x00010000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_SHIFT    16
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: failover_on_intr [15:15] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_MASK      0x00008000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_SHIFT     15
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: ubus_err_intr [14:14] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_MASK         0x00004000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_SHIFT        14
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: gisb_err_intr [13:13] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_MASK         0x00002000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_SHIFT        13
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: mdio_done_intr [12:12] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_MASK        0x00001000
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_SHIFT       12
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: mdio_err_up_intr [11:11] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_MASK      0x00000800
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_SHIFT     11
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: 1588_intr [10:10] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_MASK             0x00000400
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_SHIFT            10
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p7_cpu_wake_timer_intr [09:09] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p8_cpu_wake_timer_intr [08:08] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p5_cpu_wake_timer_intr [07:07] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: eee_lpi_intr [06:06] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_MASK          0x00000040
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_SHIFT         6
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: memory_double_err_intr [05:05] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_MASK          0x00000010
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_SHIFT         4
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_MASK    0x00000008
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_SHIFT   3
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_MASK     0x00000004
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_SHIFT    2
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_MASK     0x00000002
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_SHIFT    1
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_MASK       0x00000001
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_SHIFT      0
#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_DEFAULT    0x00000000

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: PCI_SET :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_reserved0_MASK                0xfffc0000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_reserved0_SHIFT               18

/* SWITCH_INTRL2_0 :: PCI_SET :: TCAM_soft_err_intr [17:17] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_TCAM_soft_err_intr_MASK       0x00020000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_TCAM_soft_err_intr_SHIFT      17
#define BCHP_SWITCH_INTRL2_0_PCI_SET_TCAM_soft_err_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: failover_off_intr [16:16] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_MASK        0x00010000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_SHIFT       16
#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: failover_on_intr [15:15] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_MASK         0x00008000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_SHIFT        15
#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: ubus_err_intr [14:14] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_MASK            0x00004000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_SHIFT           14
#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_DEFAULT         0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: gisb_err_intr [13:13] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_MASK            0x00002000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_SHIFT           13
#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_DEFAULT         0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: mdio_done_intr [12:12] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_MASK           0x00001000
#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_SHIFT          12
#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: mdio_err_up_intr [11:11] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_MASK         0x00000800
#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_SHIFT        11
#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: 1588_intr [10:10] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_MASK                0x00000400
#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_SHIFT               10
#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_DEFAULT             0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p7_cpu_wake_timer_intr [09:09] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_MASK   0x00000200
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_SHIFT  9
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p8_cpu_wake_timer_intr [08:08] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_MASK   0x00000100
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_SHIFT  8
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p5_cpu_wake_timer_intr [07:07] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_MASK   0x00000080
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_SHIFT  7
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: eee_lpi_intr [06:06] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_MASK             0x00000040
#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_SHIFT            6
#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: memory_double_err_intr [05:05] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_MASK   0x00000020
#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_SHIFT  5
#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p0_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_MASK             0x00000010
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_SHIFT            4
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p0_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_MASK       0x00000008
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_SHIFT      3
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p0_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_MASK        0x00000004
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_SHIFT       2
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p0_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_MASK        0x00000002
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_SHIFT       1
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_0 :: PCI_SET :: p0_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_MASK          0x00000001
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_SHIFT         0
#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_DEFAULT       0x00000000

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: PCI_CLEAR :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_reserved0_MASK              0xfffc0000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_reserved0_SHIFT             18

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: TCAM_soft_err_intr [17:17] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_TCAM_soft_err_intr_MASK     0x00020000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_TCAM_soft_err_intr_SHIFT    17
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_TCAM_soft_err_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: failover_off_intr [16:16] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_MASK      0x00010000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_SHIFT     16
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: failover_on_intr [15:15] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_MASK       0x00008000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_SHIFT      15
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: ubus_err_intr [14:14] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_MASK          0x00004000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_SHIFT         14
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: gisb_err_intr [13:13] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_MASK          0x00002000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_SHIFT         13
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: mdio_done_intr [12:12] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_MASK         0x00001000
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_SHIFT        12
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_DEFAULT      0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: mdio_err_up_intr [11:11] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_MASK       0x00000800
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_SHIFT      11
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: 1588_intr [10:10] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_MASK              0x00000400
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_SHIFT             10
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_DEFAULT           0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p7_cpu_wake_timer_intr [09:09] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p8_cpu_wake_timer_intr [08:08] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p5_cpu_wake_timer_intr [07:07] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: eee_lpi_intr [06:06] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_MASK           0x00000040
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_SHIFT          6
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: memory_double_err_intr [05:05] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_MASK           0x00000010
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_SHIFT          4
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_MASK     0x00000008
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_SHIFT    3
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_MASK      0x00000004
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_SHIFT     2
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_MASK      0x00000002
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_SHIFT     1
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_MASK        0x00000001
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_SHIFT       0
#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_DEFAULT     0x00000000

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_reserved0_MASK        0xfffc0000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_reserved0_SHIFT       18

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: TCAM_soft_err_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_TCAM_soft_err_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_TCAM_soft_err_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_TCAM_soft_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: failover_off_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: failover_on_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: ubus_err_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: gisb_err_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: mdio_done_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: mdio_err_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: 1588_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_MASK   0x00000400
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_SHIFT  10
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p7_cpu_wake_timer_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p8_cpu_wake_timer_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p5_cpu_wake_timer_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: eee_lpi_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: memory_double_err_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_reserved0_MASK           0xfffc0000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_reserved0_SHIFT          18

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: TCAM_soft_err_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_TCAM_soft_err_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_TCAM_soft_err_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_TCAM_soft_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: failover_off_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: failover_on_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: ubus_err_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_MASK  0x00004000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: gisb_err_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_MASK  0x00002000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: mdio_done_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: mdio_err_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_MASK  0x00000800
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: 1588_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_MASK      0x00000400
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_SHIFT     10
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_DEFAULT   0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p7_cpu_wake_timer_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p8_cpu_wake_timer_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p5_cpu_wake_timer_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: eee_lpi_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_MASK   0x00000040
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_SHIFT  6
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: memory_double_err_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_MASK   0x00000010
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_SHIFT  4
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: reserved0 [31:18] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_reserved0_MASK         0xfffc0000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_reserved0_SHIFT        18

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: TCAM_soft_err_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_TCAM_soft_err_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_TCAM_soft_err_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_TCAM_soft_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: failover_off_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: failover_on_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: ubus_err_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: gisb_err_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: mdio_done_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: mdio_err_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: 1588_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_MASK    0x00000400
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_SHIFT   10
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p7_cpu_wake_timer_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p8_cpu_wake_timer_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p5_cpu_wake_timer_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: eee_lpi_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: memory_double_err_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_DEFAULT 0x00000001

#endif /* #ifndef BCHP_SWITCH_INTRL2_0_H__ */

/* End of File */