blob: b2069ff8f8080f0000ced29a4685c482823c7788 [file] [log] [blame]
/***************************************************************************
* Copyright (c) 1999-2013, Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Fri Oct 25 17:33:25 2013
* Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
* (minus title and desc)
* MD5 Checksum 383dbfcd91460427fa61afa66d6c98f8
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.008005
* Operating System linux
*
* Revision History:
*
* $brcm_Log: $
*
***************************************************************************/
#ifndef BCHP_HIF_INTR2_H__
#define BCHP_HIF_INTR2_H__
/***************************************************************************
*HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
***************************************************************************/
#define BCHP_HIF_INTR2_CPU_STATUS 0x204a1000 /* CPU interrupt Status Register */
#define BCHP_HIF_INTR2_CPU_SET 0x204a1004 /* CPU interrupt Set Register */
#define BCHP_HIF_INTR2_CPU_CLEAR 0x204a1008 /* CPU interrupt Clear Register */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS 0x204a100c /* CPU interrupt Mask Status Register */
#define BCHP_HIF_INTR2_CPU_MASK_SET 0x204a1010 /* CPU interrupt Mask Set Register */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR 0x204a1014 /* CPU interrupt Mask Clear Register */
#define BCHP_HIF_INTR2_PCI_STATUS 0x204a1018 /* PCI interrupt Status Register */
#define BCHP_HIF_INTR2_PCI_SET 0x204a101c /* PCI interrupt Set Register */
#define BCHP_HIF_INTR2_PCI_CLEAR 0x204a1020 /* PCI interrupt Clear Register */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS 0x204a1024 /* PCI interrupt Mask Status Register */
#define BCHP_HIF_INTR2_PCI_MASK_SET 0x204a1028 /* PCI interrupt Mask Set Register */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR 0x204a102c /* PCI interrupt Mask Clear Register */
/***************************************************************************
*CPU_STATUS - CPU interrupt Status Register
***************************************************************************/
/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT 28
/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT 18
/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT 6
/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT 2
/* HIF_INTR2 :: CPU_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
/***************************************************************************
*CPU_SET - CPU interrupt Set Register
***************************************************************************/
/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT 28
/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT 18
/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT 6
/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT 2
/* HIF_INTR2 :: CPU_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
/***************************************************************************
*CPU_CLEAR - CPU interrupt Clear Register
***************************************************************************/
/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT 28
/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT 18
/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT 6
/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT 2
/* HIF_INTR2 :: CPU_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
/***************************************************************************
*CPU_MASK_STATUS - CPU interrupt Mask Status Register
***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 28
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT 18
/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT 6
/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT 2
/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
/***************************************************************************
*CPU_MASK_SET - CPU interrupt Mask Set Register
***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT 28
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT 18
/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT 6
/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT 2
/* HIF_INTR2 :: CPU_MASK_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
/***************************************************************************
*CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 28
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT 18
/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT 6
/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT 2
/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
/***************************************************************************
*PCI_STATUS - PCI interrupt Status Register
***************************************************************************/
/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT 28
/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT 18
/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT 6
/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT 2
/* HIF_INTR2 :: PCI_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
/***************************************************************************
*PCI_SET - PCI interrupt Set Register
***************************************************************************/
/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT 28
/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT 18
/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT 6
/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT 2
/* HIF_INTR2 :: PCI_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
/***************************************************************************
*PCI_CLEAR - PCI interrupt Clear Register
***************************************************************************/
/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT 28
/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT 18
/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT 6
/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT 2
/* HIF_INTR2 :: PCI_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000000
/***************************************************************************
*PCI_MASK_STATUS - PCI interrupt Mask Status Register
***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 28
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT 18
/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT 6
/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT 2
/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
/***************************************************************************
*PCI_MASK_SET - PCI interrupt Mask Set Register
***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT 28
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT 18
/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT 6
/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT 2
/* HIF_INTR2 :: PCI_MASK_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
/***************************************************************************
*PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xf0000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 28
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:18] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK 0x000c0000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT 18
/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT 15
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:06] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK 0x00007fc0
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT 6
/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT 5
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT 4
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT 2
/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_SHIFT 1
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT 0x00000001
/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
#endif /* #ifndef BCHP_HIF_INTR2_H__ */
/* End of File */