/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Wed Sep  3 12:36:27 2014
 *                 Full Compile MD5 Checksum 1e5d73e2e037f01f6ffd5061d00a97a7
 *                   (minus title and desc)  
 *                 MD5 Checksum              c8f174845d8a27ef5365467f1c7a712b
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008005
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_CLKGEN_H__
#define BCHP_CLKGEN_H__

/***************************************************************************
 *CLKGEN - clkgen registers
 ***************************************************************************/
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON 0x20460000 /* Bandgap Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x20460004 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x20460008 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x2046000c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x20460010 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x20460014 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x20460018 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV      0x2046001c /* Pre multiplier */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN     0x20460020 /* PLL GAIN */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL 0x20460024 /* Hold PLL all channels */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL 0x20460028 /* Ldo voltage control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON 0x2046002c /* LDO Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS 0x20460030 /* Lock Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC     0x20460034 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2    0x20460038 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON    0x2046003c /* Poweron */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET    0x20460040 /* Resets */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x20460044 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x20460048 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS   0x2046004c /* Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON 0x20460050 /* Bandgap Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x20460054 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x20460058 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x2046005c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x20460060 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x20460064 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 0x20460068 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV      0x2046006c /* Pre multiplier */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN     0x20460070 /* PLL GAIN */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL 0x20460074 /* Hold PLL all channels */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL 0x20460078 /* Ldo voltage control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON 0x2046007c /* LDO Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS 0x20460080 /* Lock Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC     0x20460084 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2    0x20460088 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON    0x2046008c /* Poweron */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET    0x20460090 /* Resets */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x20460094 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x20460098 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS   0x2046009c /* Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON 0x204600a0 /* Bandgap Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 0x204600a4 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV      0x204600a8 /* Pre multiplier */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN     0x204600ac /* PLL GAIN */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL 0x204600b0 /* Hold PLL all channels */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL 0x204600b4 /* Ldo voltage control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON 0x204600b8 /* LDO Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS 0x204600bc /* Lock Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC     0x204600c0 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2    0x204600c4 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON    0x204600c8 /* Poweron */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET    0x204600cc /* Resets */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH 0x204600d0 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW 0x204600d4 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS   0x204600d8 /* Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x204600dc /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x204600e0 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x204600e4 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3 0x204600e8 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4 0x204600ec /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x204600f0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x204600f4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON        0x204600f8 /* LDO Power on */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x204600fc /* Lock Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x20460100 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x20460104 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON            0x20460108 /* Poweron */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x2046010c /* Resets */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x20460110 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x20460114 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x20460118 /* Status */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 0x2046011c /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 0x20460120 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 0x20460124 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV         0x20460128 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC        0x2046012c /* Fractional */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN        0x20460130 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON   0x20460134 /* LDO Power on */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS 0x20460138 /* Lock Status */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC        0x2046013c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2       0x20460140 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON       0x20460144 /* Poweron */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET       0x20460148 /* Resets */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH 0x2046014c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW 0x20460150 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS      0x20460154 /* Status */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x20460158 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x2046015c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x20460160 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3 0x20460164 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL           0x20460168 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV               0x2046016c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN              0x20460170 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL       0x20460174 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL          0x20460178 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON         0x2046017c /* LDO Power on */
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS       0x20460180 /* Lock Status */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC              0x20460184 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2             0x20460188 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL        0x2046018c /* selection of the output clock from the PLL core */
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON             0x20460190 /* Poweron */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET             0x20460194 /* Resets */
#define BCHP_CLKGEN_PLL_LC_PLL_STATUS            0x20460198 /* Status */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST              0x2046019c /* enable and selection pf PLL test */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x204601a0 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x204601a4 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x204601a8 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x204601ac /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x204601b0 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x204601b4 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x204601b8 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x204601bc /* PLL GAIN */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON       0x204601c0 /* LDO Power on */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x204601c4 /* Lock Status */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x204601c8 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x204601cc /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON           0x204601d0 /* Poweron */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x204601d4 /* Resets */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x204601d8 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x204601dc /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x204601e0 /* Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x204601e4 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x204601e8 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 0x204601ec /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 0x204601f0 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 0x204601f4 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 0x204601f8 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x204601fc /* Pre multiplier */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x20460200 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON      0x20460204 /* LDO Power on */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x20460208 /* Lock Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x2046020c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x20460210 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON          0x20460214 /* Poweron */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x20460218 /* Resets */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x2046021c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x20460220 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x20460224 /* Status */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x20460228 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV              0x2046022c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC             0x20460230 /* Fractional */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN             0x20460234 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS      0x20460238 /* Lock Status */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC             0x2046023c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2            0x20460240 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON            0x20460244 /* Poweron */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET            0x20460248 /* Resets */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x2046024c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x20460250 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS           0x20460254 /* Status */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x20460258 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV              0x2046025c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC             0x20460260 /* Fractional */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN             0x20460264 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS      0x20460268 /* Lock Status */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC             0x2046026c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2            0x20460270 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON            0x20460274 /* Poweron */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET            0x20460278 /* Resets */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x2046027c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x20460280 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS           0x20460284 /* Status */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 0x20460288 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 0x2046028c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 0x20460290 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 0x20460294 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV           0x20460298 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN          0x2046029c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON     0x204602a0 /* LDO Power on */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS   0x204602a4 /* Lock Status */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC          0x204602a8 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2         0x204602ac /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON         0x204602b0 /* Poweron */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET         0x204602b4 /* Resets */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH 0x204602b8 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW 0x204602bc /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS        0x204602c0 /* Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON        0x204602c4 /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x204602c8 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x204602cc /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x204602d0 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x204602d4 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x204602d8 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x204602dc /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x204602e0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x204602e4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL     0x204602e8 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL        0x204602ec /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON       0x204602f0 /* LDO Power on */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x204602f4 /* Lock Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x204602f8 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x204602fc /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON           0x20460300 /* Poweron */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x20460304 /* Resets */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x20460308 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x2046030c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x20460310 /* Status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON       0x20460314 /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x20460318 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x2046031c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x20460320 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x20460324 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x20460328 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x2046032c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL    0x20460330 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL       0x20460334 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON      0x20460338 /* LDO Power on */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x2046033c /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x20460340 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2          0x20460344 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON          0x20460348 /* Poweron */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x2046034c /* Resets */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x20460350 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x20460354 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x20460358 /* Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON       0x2046035c /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x20460360 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x20460364 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x20460368 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x2046036c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x20460370 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x20460374 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL    0x20460378 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL       0x2046037c /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON      0x20460380 /* LDO Power on */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x20460384 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x20460388 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2          0x2046038c /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON          0x20460390 /* Poweron */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x20460394 /* Resets */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x20460398 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x2046039c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x204603a0 /* Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON       0x204603a4 /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x204603a8 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x204603ac /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x204603b0 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV            0x204603b4 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC           0x204603b8 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN           0x204603bc /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL    0x204603c0 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL       0x204603c4 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON      0x204603c8 /* LDO Power on */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS    0x204603cc /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC           0x204603d0 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2          0x204603d4 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON          0x204603d8 /* Poweron */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET          0x204603dc /* Resets */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x204603e0 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x204603e4 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS         0x204603e8 /* Status */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x204603ec /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x204603f0 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x204603f4 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x204603f8 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x204603fc /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5 0x20460400 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV              0x20460404 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN             0x20460408 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON        0x2046040c /* LDO Power on */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS      0x20460410 /* Lock Status */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC             0x20460414 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2            0x20460418 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON            0x2046041c /* Poweron */
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET            0x20460420 /* Resets */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x20460424 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x20460428 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS           0x2046042c /* Status */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x20460430 /* Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x20460434 /* Clock Disable Status */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x20460438 /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x2046043c /* Clock Disable Status */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE 0x20460440 /* Disable APM_CHIP_TOP_INST's clocks */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS 0x20460444 /* Clock Disable Status */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE 0x20460448 /* Apm chip top inst clock enable */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS 0x2046044c /* Clock Enable Status */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x20460450 /* Bvn mvp top inst clock enable */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x20460454 /* Clock Enable Status */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x20460458 /* Bvn top inst clock enable */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x2046045c /* Clock Enable Status */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x20460460 /* Disable CLKGEN's clocks */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS  0x20460464 /* Clock Disable Status */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE     0x20460468 /* Clkgen inst clock enable */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS 0x2046046c /* Clock Enable Status */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_SELECT     0x20460470 /* Clkgen inst clock select */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x20460474 /* Clock Monitor Control */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x20460478 /* Clock Monitor Max Reference Count */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x2046047c /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x20460480 /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x20460484 /* Clock Monitor View Counter */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE 0x20460488 /* Disable CORE_XPT_HIF_INST's clocks */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS 0x2046048c /* Clock Disable Status */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE 0x20460490 /* Core xpt hif inst clock enable */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS 0x20460494 /* Clock Enable Status */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK 0x20460498 /* Core xpt hif inst observe clock */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE 0x2046049c /* Disable CPU4355_BCM_MIPS_TOP_INST's clocks */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS 0x204604a0 /* Clock Disable Status */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE 0x204604a4 /* Cpu4355 bcm mips top inst clock enable */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS 0x204604a8 /* Clock Enable Status */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE 0x204604ac /* Disable D3DSMAC_X4_TOP_INST's clocks */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS 0x204604b0 /* Clock Disable Status */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE 0x204604b4 /* D3dsmac x4 top inst clock enable */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS 0x204604b8 /* Clock Enable Status */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE 0x204604bc /* Disable DECT_UBUS_TOP_INST's clocks */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS 0x204604c0 /* Clock Disable Status */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE 0x204604c4 /* Dect ubus top inst clock enable */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS 0x204604c8 /* Clock Enable Status */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2    0x204604cc /* Disable AVS_TOP 54MHz clocks during S2 standby. */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x204604d0 /* Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL 0x204604d4 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL 0x204604d8 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS 0x204604dc /* DOCSIS_PLL_SYS2 Reset Status */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE   0x204604e0 /* Disable DS_TOPA_INST's clocks */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_STATUS 0x204604e4 /* Clock Disable Status */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE    0x204604e8 /* Ds topa inst clock enable */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS 0x204604ec /* Clock Enable Status */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE   0x204604f0 /* Disable DS_TOPB_INST's clocks */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_STATUS 0x204604f4 /* Clock Disable Status */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE    0x204604f8 /* Ds topb inst clock enable */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS 0x204604fc /* Clock Enable Status */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE   0x20460500 /* Disable DS_TOPC_INST's clocks */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_STATUS 0x20460504 /* Clock Disable Status */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE    0x20460508 /* Ds topc inst clock enable */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS 0x2046050c /* Clock Enable Status */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE   0x20460510 /* Disable DS_TOPD_INST's clocks */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_STATUS 0x20460514 /* Clock Disable Status */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE    0x20460518 /* Ds topd inst clock enable */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS 0x2046051c /* Clock Enable Status */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE 0x20460520 /* Disable DS_WFE_TOP_INST's clocks */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS 0x20460524 /* Clock Disable Status */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE 0x20460528 /* Ds wfe top inst clock enable */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS 0x2046052c /* Clock Enable Status */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE 0x20460530 /* Disable DTP_DFAP_TOP_INST's clocks */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x20460534 /* Clock Disable Status */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE 0x20460538 /* Dtp dfap top inst clock enable */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x2046053c /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE    0x20460540 /* Disable DVP_HR_INST's clocks */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x20460544 /* Clock Disable Status */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x20460548 /* Dvp hr inst clock enable */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x2046054c /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x20460550 /* Dvp hr inst observe clock */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x20460554 /* Disable DVP_HT_INST's clocks */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x20460558 /* Clock Disable Status */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x2046055c /* Dvp ht inst clock enable */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x20460560 /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x20460564 /* Dvp ht inst observe clock */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE 0x20460568 /* Disable EAGLET_TOP_INST's clocks */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS 0x2046056c /* Clock Disable Status */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE 0x20460570 /* Eaglet top inst clock enable */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS 0x20460574 /* Clock Enable Status */
#define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE       0x20460578 /* Eaglet top inst enable */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT 0x2046057c /* Egphy28 4port 33v 90o fc inst clock select */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE 0x20460580 /* G2u u2u ubus mod ss inst clock enable */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS 0x20460584 /* Clock Enable Status */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE  0x20460588 /* Disable GFAP_TOP_INST's clocks */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x2046058c /* Clock Disable Status */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE   0x20460590 /* Gfap top inst clock enable */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0  0x20460594 /* Gfap top inst clock enable0 */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS 0x20460598 /* Clock Enable Status */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x2046059c /* Clock Enable Status */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE   0x204605a0 /* Hvd0 top inst clock enable */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x204605a4 /* Clock Enable Status */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK  0x204605a8 /* Hvd0 top inst observe clock */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE 0x204605ac /* Hvd sid1 top inst clock enable */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID 0x204605b0 /* Hvd sid1 top inst clock enable sid */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x204605b4 /* Clock Enable Status */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS 0x204605b8 /* Clock Enable Status */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK 0x204605bc /* Hvd sid1 top inst observe clock */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x204605c0 /* Mux selects for Internal clocks */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT          0x204605c4 /* Mux selects for itu656_0 clocks */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE  0x204605c8 /* Disable LEAP_TOP_INST's clocks */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS 0x204605cc /* Clock Disable Status */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE   0x204605d0 /* Leap top inst clock enable */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS 0x204605d4 /* Clock Enable Status */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK  0x204605d8 /* Leap top inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE 0x204605dc /* Memsys 32 wrapper 0 inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS 0x204605e0 /* Clock Enable Status */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK 0x204605e4 /* Memsys 32 wrapper 0 inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS 0x204605e8 /* Memsys 32 wrapper 0 inst status */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE 0x204605ec /* Memsys 32 wrapper 1 inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS 0x204605f0 /* Clock Enable Status */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK 0x204605f4 /* Memsys 32 wrapper 1 inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS 0x204605f8 /* Memsys 32 wrapper 1 inst status */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x204605fc /* Mocamac top inst clock enable */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x20460600 /* Clock Enable Status */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x20460604 /* Mocamac top inst observe clock */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x20460608 /* Mocaphy top inst clock enable */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x2046060c /* Clock Enable Status */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x20460610 /* Mocaphy top inst observe clock */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE          0x20460614 /* Disable MULTI's clocks */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS   0x20460618 /* Clock Disable Status */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION     0x2046061c /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION     0x20460620 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x20460624 /* Disable PAD's clocks */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS     0x20460628 /* Clock Disable Status */
#define BCHP_CLKGEN_PAD_MUX_SELECT               0x2046062c /* Mux selects for Pad clocks */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE 0x20460630 /* Disable PCIE_X2_TOP_INST's clocks */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS 0x20460634 /* Clock Disable Status */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE 0x20460638 /* Pcie x2 top inst clock enable */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS 0x2046063c /* Clock Enable Status */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK 0x20460640 /* Pcie x2 top inst observe clock */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x20460644 /* PLL_AVD Reset Status */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL       0x20460648 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST 0x2046064c /* PLL_CPU_CORE Glitchless Clock Switching */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS 0x20460650 /* PLL_CPU_CORE Glitchless Switching */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS 0x20460654 /* PLL_CPU_CORE Reset Status */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL  0x20460658 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS      0x2046065c /* PLL_LC Reset Status */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL        0x20460660 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x20460664 /* PLL_MOCA Reset Status */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x20460668 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x2046066c /* PLL_RAAGA Reset Status */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x20460670 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS     0x20460674 /* PLL_SC0 Reset Status */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL       0x20460678 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS     0x2046067c /* PLL_SC1 Reset Status */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL       0x20460680 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x20460684 /* Disable */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS  0x20460688 /* PLL_SWITCH Reset Status */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL      0x2046068c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x20460690 /* PLL_VCXO0 Reset Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x20460694 /* PLL_VCXO1 Reset Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS   0x20460698 /* PLL_VCXO2 Reset Status */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL       0x2046069c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL     0x204606a0 /* Select clocks that can stay alive during power management standby mode. */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x204606a4 /* PLL Alive in Standby Mode */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x204606a8 /* Power management LDO PLL */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE  0x204606ac /* Disable PROD_OTP_INST's clocks */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x204606b0 /* Clock Disable Status */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE   0x204606b4 /* Prod otp inst clock enable */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x204606b8 /* Clock Enable Status */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x204606bc /* Raaga dsp top 0 inst clock enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x204606c0 /* Clock Enable Status */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x204606c4 /* Raaga dsp top 0 inst observe clock */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE 0x204606c8 /* Raaga dsp top 1 inst clock enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS 0x204606cc /* Clock Enable Status */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK 0x204606d0 /* Raaga dsp top 1 inst observe clock */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE    0x204606d4 /* Rfm top inst clock enable */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x204606d8 /* Clock Enable Status */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK   0x204606dc /* Rfm top inst observe clock */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE 0x204606e0 /* Disable SATA3_TOP_0_INST's clocks */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS 0x204606e4 /* Clock Disable Status */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE 0x204606e8 /* Sata3 top 0 inst clock enable */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS 0x204606ec /* Clock Enable Status */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_SELECT 0x204606f0 /* Sata3 top 0 inst clock select */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK 0x204606f4 /* Sata3 top 0 inst observe clock */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE 0x204606f8 /* Disable SATA3_TOP_1_INST's clocks */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS 0x204606fc /* Clock Disable Status */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE 0x20460700 /* Sata3 top 1 inst clock enable */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS 0x20460704 /* Clock Enable Status */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_SELECT 0x20460708 /* Sata3 top 1 inst clock select */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK 0x2046070c /* Sata3 top 1 inst observe clock */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x20460710 /* Sectop inst observe clock */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x20460714 /* Mux selects for Smartcard clocks */
#define BCHP_CLKGEN_SPARE                        0x20460718 /* Spares */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE 0x2046071c /* Disable SWITCH_TOP_INST's clocks */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS 0x20460720 /* Clock Disable Status */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE 0x20460724 /* Switch top inst clock enable */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS 0x20460728 /* Clock Enable Status */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK 0x2046072c /* Switch top inst observe clock */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x20460730 /* Disable SYS_CTRL_INST's clocks */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x20460734 /* Clock Disable Status */
#define BCHP_CLKGEN_TESTPORT                     0x20460738 /* Special Testport Controls */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE 0x2046073c /* Disable UBUS_MOD_PERIPH_FPM_INST's clocks */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS 0x20460740 /* Clock Disable Status */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE 0x20460744 /* Ubus mod periph fpm inst clock enable */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS 0x20460748 /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE 0x2046074c /* Disable UNIMAC_MBDMA_TOP_ROUTER_1_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS 0x20460750 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE 0x20460754 /* Unimac mbdma top router 1 inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS 0x20460758 /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE 0x2046075c /* Disable UNIMAC_MBDMA_TOP_ROUTER_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS 0x20460760 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE 0x20460764 /* Unimac mbdma top router inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS 0x20460768 /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE 0x2046076c /* Disable UNIMAC_MBDMA_TOP_STB_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS 0x20460770 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE 0x20460774 /* Unimac mbdma top stb inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS 0x20460778 /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE 0x2046077c /* Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS 0x20460780 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE 0x20460784 /* Unimac mbdma top wan inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS 0x20460788 /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE  0x2046078c /* Disable USB0_TOP_INST's clocks */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS 0x20460790 /* Clock Disable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE   0x20460794 /* Usb0 top inst clock enable */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x20460798 /* Usb0 top inst clock enable ahb */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x2046079c /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x204607a0 /* Usb0 top inst clock enable axi */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x204607a4 /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x204607a8 /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK  0x204607ac /* Usb0 top inst observe clock */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE 0x204607b0 /* Disable USMAC_TC8X_DAVIC_TOP_INST's clocks */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS 0x204607b4 /* Clock Disable Status */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE 0x204607b8 /* Usmac tc8x davic top inst clock enable */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS 0x204607bc /* Clock Enable Status */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE     0x204607c0 /* Us top inst clock enable */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS 0x204607c4 /* Clock Enable Status */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE 0x204607c8 /* Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS 0x204607cc /* Clock Disable Status */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE 0x204607d0 /* Utp crypto segdma top inst clock enable */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS 0x204607d4 /* Clock Enable Status */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE    0x204607d8 /* V3d top inst clock enable */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x204607dc /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE 0x204607e0 /* Disable VEC_AIO_GFX_TOP_INST's clocks */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS 0x204607e4 /* Clock Disable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE 0x204607e8 /* Vec aio gfx top inst clock enable */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO 0x204607ec /* Vec aio gfx top inst clock enable aio */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x204607f0 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0 0x204607f4 /* Vec aio gfx top inst clock enable m2mc0 */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS 0x204607f8 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1 0x204607fc /* Vec aio gfx top inst clock enable m2mc1 */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS 0x20460800 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS 0x20460804 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT 0x20460808 /* Vec aio gfx top inst clock enable systemport */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS 0x2046080c /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC 0x20460810 /* Vec aio gfx top inst clock enable vec */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF 0x20460814 /* Vec aio gfx top inst clock enable vec qdac intf */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS 0x20460818 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x2046081c /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK 0x20460820 /* Vec aio gfx top inst observe clock */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE    0x20460824 /* Vice2 0 inst clock enable */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS 0x20460828 /* Clock Enable Status */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE    0x2046082c /* Vice2 1 inst clock enable */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS 0x20460830 /* Clock Enable Status */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x20460834 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 0x20460838 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL 0x2046083c /* AVD_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL 0x20460840 /* MOCA_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL 0x20460844 /* SWITCH_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL 0x20460848 /* RAAGA_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL 0x2046084c /* VCXO0_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL 0x20460850 /* VCXO1_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL 0x20460854 /* VCXO2_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL  0x20460858 /* LC_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL 0x2046085c /* SC0_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL 0x20460860 /* SC1_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL 0x20460864 /* SYS0_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL 0x20460868 /* XPT_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL 0x2046086c /* CPU_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL 0x20460870 /* DOCSISSYS0_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL 0x20460874 /* DOCSISSYS1_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL 0x20460878 /* DOCSISSYS2_PLL_CTRL_WRAPPER control */
#define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT 0x2046087c /* core_xpt_hif inst byp clock select */
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON        0x20460880 /* LDO Power on */
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON        0x20460884 /* LDO Power on */

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT   1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000c

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000e

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000090

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000d

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000000e

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_MASK         0xffffc000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_SHIFT        14

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_MASK              0x00003c00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_SHIFT             10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_DEFAULT           0x00000002

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_MASK          0x000003ff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT       0x00000090

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_MASK        0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_SHIFT       10

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK    0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT   16

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK     0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT    0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT  0x00005005

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT  1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK      0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT     0

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK    0x80000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT   31
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK   0x40000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT  30
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT        29
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK      0x10000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT     28
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK      0x0e000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT     25
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_MASK       0x01000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT      24
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT    0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_MASK        0x00c00000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT       22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK     0x00200000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT    21
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT  0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_MASK         0x00180000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT        19
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT      0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK      0x00010000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT     16
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK        0x00008000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT       15
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK   0x00004000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT  14
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK  0x00001ffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK         0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT        0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT      0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT   1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK   0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT  0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_MASK          0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_DEFAULT       0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_SHIFT     12

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK    0x00000fff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT   0

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_SHIFT   1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000005

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000024

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000c

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000000a

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_MASK         0xffffc000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_SHIFT        14

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_MASK              0x00003c00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_SHIFT             10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_DEFAULT           0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_MASK          0x000003ff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT       0x000000c8

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_MASK        0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_SHIFT       10

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_MASK    0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_SHIFT   16

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_MASK     0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_SHIFT    0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT  0x00005005

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_SHIFT  1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK      0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT     0

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_MASK    0x80000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_SHIFT   31
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_MASK   0x40000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_SHIFT  30
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_SHIFT        29
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK      0x10000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT     28
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK      0x0e000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT     25
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_MASK       0x01000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_SHIFT      24
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_DEFAULT    0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_MASK        0x00c00000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT       22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_MASK     0x00200000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_SHIFT    21
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_DEFAULT  0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_MASK         0x00180000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT        19
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT      0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK      0x00010000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT     16
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK        0x00008000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT       15
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_MASK   0x00004000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_SHIFT  14
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK  0x00001ffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK         0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT        0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT      0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_SHIFT   1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_MASK   0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_SHIFT  0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_MASK          0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_DEFAULT       0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_SHIFT     12

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK    0x00000fff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT   0

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_SHIFT   1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_MASK         0xffffc000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_SHIFT        14

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_MASK              0x00003c00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_SHIFT             10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_DEFAULT           0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_MASK          0x000003ff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_DEFAULT       0x0000007d

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_MASK        0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_SHIFT       10

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_MASK    0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_SHIFT   16

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_MASK     0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_SHIFT    0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT  0x00005005

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_SHIFT  1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_MASK      0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_SHIFT     0

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_MASK    0x80000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_SHIFT   31
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_MASK   0x40000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_SHIFT  30
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_SHIFT        29
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_MASK      0x10000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_SHIFT     28
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_MASK      0x0e000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_SHIFT     25
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_MASK       0x01000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_SHIFT      24
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_DEFAULT    0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_MASK        0x00c00000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_SHIFT       22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_MASK     0x00200000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_SHIFT    21
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_DEFAULT  0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_MASK         0x00180000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_SHIFT        19
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_DEFAULT      0x00000002

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_MASK      0x00010000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_SHIFT     16
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_MASK        0x00008000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_SHIFT       15
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_MASK   0x00004000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_SHIFT  14
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_MASK  0x00001ffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_MASK         0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_SHIFT        0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_DEFAULT      0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_SHIFT   1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_MASK   0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_SHIFT  0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_SHIFT      2

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_MASK          0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_SHIFT         1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_DEFAULT       0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_MASK          0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_DEFAULT       0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_SHIFT     12

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_MASK    0x00000fff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_SHIFT   0

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000006

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   0x00000003

/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               0x000000c8

/***************************************************************************
 *PLL_AVD_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_AVD_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_AVD_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_AVD_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_AVD_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002

/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_AVD_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_AVD_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_AVD_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_AVD_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0x00000000

/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0x00000000

/***************************************************************************
 *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000064

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_MASK            0xffffc000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_SHIFT           14

/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_MASK                 0x00003c00
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_SHIFT                10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_DEFAULT              0x00000003

/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_MASK             0x000003ff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_SHIFT            0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7

/***************************************************************************
 *PLL_CPU_CORE_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_MASK           0xfff00000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_SHIFT          20

/* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_MASK        0x000fffff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_SHIFT       0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_DEFAULT     0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_MASK           0xfffffc00
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_SHIFT          10

/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x00000038
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  3
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_CPU_CORE_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_SHIFT     1

/* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK  0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_SHIFT   2

/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1

/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_SHIFT        0

/***************************************************************************
 *PLL_CPU_CORE_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_MASK           0xc0000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_SHIFT          30
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_DEFAULT        0x00000002

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_SHIFT        29
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_DEFAULT      0x00000001

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_MASK         0x10000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_SHIFT        28
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_MASK         0x0e000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_SHIFT        25
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_MASK          0x01000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_SHIFT         24
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_DEFAULT       0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_MASK           0x00c00000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_SHIFT          22
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_DEFAULT        0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_MASK            0x00300000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_SHIFT           20
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_MASK    0x000c0000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_SHIFT   18
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_MASK        0x00030000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_SHIFT       16
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_DEFAULT     0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_MASK        0x00008000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_SHIFT       15
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_DEFAULT     0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_MASK         0x00004000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_SHIFT        14
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_MASK           0x00002000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_SHIFT          13
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00000fff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_SHIFT      2
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_DEFAULT    0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_MASK                0x00000003
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_SHIFT               0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_DEFAULT             0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_MASK          0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_SHIFT         0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_DEFAULT       0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_SHIFT         2

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_MASK             0x00000002
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_SHIFT            1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_DEFAULT          0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_MASK             0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_SHIFT            0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_DEFAULT          0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_MASK         0xfffff000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_SHIFT        12

/* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_SHIFT      0

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x0000006c

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x0000002d

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  0x00000036

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000036

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT             1

/* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT               0
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000

/***************************************************************************
 *PLL_LC_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK                  0xffffc000
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT                 14

/* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK                       0x00003c00
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT                      10
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT                    0x00000002

/* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT                  0
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT                0x00000064

/***************************************************************************
 *PLL_LC_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK                 0xffffff80
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT                7

/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT         1

/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT       0
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT     0x00000000

/***************************************************************************
 *PLL_LC_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK             0xffffffc0
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT            6

/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK              0x0000003f
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT             0
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT           0x00000000

/***************************************************************************
 *PLL_LC_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT       0
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT     0x00000001

/***************************************************************************
 *PLL_LC_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT         1

/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT              0

/***************************************************************************
 *PLL_LC_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK          0x80000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT         31
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT       0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK         0x70000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT        28
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT      0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK          0x0e000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT         25
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT       0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK        0x01000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT       24
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT     0x00000001

/* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK         0x00800000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT        23
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT      0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK             0x007fff80
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT            7
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT          0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: EN_VCO_OUTPUT [06:06] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_MASK             0x00000040
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_SHIFT            6
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_DEFAULT          0x00000001

/* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK           0x00000020
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT          5
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT        0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK          0x00000010
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT         4
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT       0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK         0x0000000c
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT        2
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT      0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK       0x00000002
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT      1
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT    0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK        0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT       0
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT     0x00000001

/***************************************************************************
 *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [31:31] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK       0x80000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT      31
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT    0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [30:30] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK             0x40000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT            30
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT          0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [29:29] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK      0x20000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT     29
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT   0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [28:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK             0x1ffff800
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT            11
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT          0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [10:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK      0x00000600
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT     9
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT   0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [08:08] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK              0x00000100
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT             8
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT           0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [07:07] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK              0x00000080
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT             7
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT           0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [06:06] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK              0x00000040
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT             6
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT           0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK        0x00000030
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT       4
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT     0x00000002

/* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK            0x0000000f
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT           0
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT         0x00000000

/***************************************************************************
 *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK           0xfffffff8
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT          3

/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK          0x00000007
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT         0
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT       0x00000000

/***************************************************************************
 *PLL_LC_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK                0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT               1

/* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT               0
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT             0x00000001

/***************************************************************************
 *PLL_LC_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT               2

/* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK                   0x00000002
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT                  1
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT                0x00000000

/* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK                   0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT                  0
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT                0x00000000

/***************************************************************************
 *PLL_LC_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK             0xffffffff
#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT            0

/***************************************************************************
 *PLL_LC_PLL_TEST - enable and selection pf PLL test
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK                 0xfffffff0
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT                4

/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK                  0x0000000e
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT                 1
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT               0x00000000

/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK               0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT              0
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT            0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000012

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000007

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000006

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               14

/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00003c00
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  0x00000003

/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              0x000000c8

/***************************************************************************
 *PLL_MOCA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xfffffc00
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              10

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000038
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      3
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000000

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_MOCA_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_MOCA_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK               0xc0000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT              30
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT            0x00000002

/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK             0x20000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT            29
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT          0x00000001

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x10000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            28
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0e000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            25
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK              0x01000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT             24
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT           0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00c00000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              22
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00300000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               20
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK        0x000c0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT       18
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT     0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK            0x00030000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT           16
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT         0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK            0x00008000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT           15
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT         0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00004000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            14
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              13
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK           0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT          2
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT        0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_MASK                    0x00000003
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_SHIFT                   0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_DEFAULT                 0x00000001

/***************************************************************************
 *PLL_MOCA_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT             1

/* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT           0x00000001

/***************************************************************************
 *PLL_MOCA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0x00000000

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000b

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000b

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000064

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             0x0000008f

/***************************************************************************
 *PLL_RAAGA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_RAAGA_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_MASK              0xc0000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_SHIFT             30
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_DEFAULT           0x00000002

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_MASK            0x20000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_SHIFT           29
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_DEFAULT         0x00000001

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00300000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              20
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_MASK       0x000c0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_SHIFT      18
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_MASK           0x00030000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_SHIFT          16
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_DEFAULT        0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_MASK           0x00008000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_SHIFT          15
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_DEFAULT        0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00004000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           14
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00002000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             13
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_SHIFT         2
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_MASK                   0x00000003
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_SHIFT                  0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_DEFAULT                0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT                   0x00000002

/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT               0x00000030

/***************************************************************************
 *PLL_SC0_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK                0xfff00000
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT               20

/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT            0
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000

/***************************************************************************
 *PLL_SC0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_SC0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_SC0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_SC0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_SC0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT               0x00000000

/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT               0x00000000

/***************************************************************************
 *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT                   0x00000002

/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT               0x00000030

/***************************************************************************
 *PLL_SC1_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK                0xfff00000
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT               20

/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT            0
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000

/***************************************************************************
 *PLL_SC1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_SC1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_SC1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_SC1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_SC1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT               0x00000000

/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT               0x00000000

/***************************************************************************
 *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000005a

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000001c

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000001c

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_reserved0_MASK              0xffffc000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_reserved0_SHIFT             14

/* CLKGEN :: PLL_SWITCH_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_MASK                   0x00003c00
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_SHIFT                  10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_DEFAULT                0x00000003

/* CLKGEN :: PLL_SWITCH_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_MASK               0x000003ff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_SHIFT              0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_DEFAULT            0x0000007d

/***************************************************************************
 *PLL_SWITCH_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_reserved0_MASK             0xfffffc00
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_reserved0_SHIFT            10

/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_SWITCH_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_reserved0_SHIFT       1

/* CLKGEN :: PLL_SWITCH_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_SWITCH_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1

/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_SWITCH_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_MASK             0xc0000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_SHIFT            30
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_DEFAULT          0x00000002

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_MASK           0x20000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_SHIFT          29
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_DEFAULT        0x00000001

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_MASK           0x10000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_SHIFT          28
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_DEFAULT        0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_MASK           0x0e000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_SHIFT          25
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_DEFAULT        0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_MASK            0x01000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_SHIFT           24
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_DEFAULT         0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_MASK             0x00c00000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_SHIFT            22
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_DEFAULT          0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_MASK              0x00300000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_SHIFT             20
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_MASK      0x000c0000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_SHIFT     18
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_DEFAULT   0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_MASK          0x00030000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_SHIFT         16
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_DEFAULT       0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_MASK          0x00008000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_SHIFT         15
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_DEFAULT       0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_MASK           0x00004000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_SHIFT          14
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_DEFAULT        0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_MASK             0x00002000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_SHIFT            13
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_MASK       0x00000fff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_SHIFT      0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT    0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_SHIFT        2
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_DEFAULT      0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_MASK                  0x00000003
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_SHIFT                 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_DEFAULT               0x00000001

/***************************************************************************
 *PLL_SWITCH_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_SWITCH_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001

/***************************************************************************
 *PLL_SWITCH_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_SWITCH_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_DEFAULT            0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_DEFAULT            0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_SWITCH_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT       0
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT     0x00000001

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000006

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000012

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               14

/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00003c00
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000001

/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000048

/***************************************************************************
 *PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xfffffc00
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              10

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000038
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      3
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000000

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT       1

/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT     0
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT   0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK           0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT          16

/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK            0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT           0
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT         0x00005005

/***************************************************************************
 *PLL_SYS0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_SYS0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK           0x80000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT          31
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT        0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK          0x40000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT         30
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT       0x00000001

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK                0x20000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT               29
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT             0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x10000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            28
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0e000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            25
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_MASK              0x01000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT             24
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT           0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00c00000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              22
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK            0x00200000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT           21
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT         0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00180000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               19
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000001

/* CLKGEN :: PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK        0x00060000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT       17
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT     0x00000003

/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00008000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              15
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK          0x00004000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT         14
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT       0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT          1
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT        0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK          0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT         0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT           0x00000001

/***************************************************************************
 *PLL_SYS0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_VCXO0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             0x00000040

/***************************************************************************
 *PLL_VCXO0_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_VCXO0_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_SHIFT         16

/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00005005

/***************************************************************************
 *PLL_VCXO0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_MASK               0x20000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_SHIFT              29
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_SHIFT          21
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0x00000003

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x00008000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             15
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_SHIFT        14
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_SHIFT         1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_VCXO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_VCXO1_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             0x00000040

/***************************************************************************
 *PLL_VCXO1_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_VCXO1_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_SHIFT         16

/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00005005

/***************************************************************************
 *PLL_VCXO1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_MASK               0x20000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_SHIFT              29
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_SHIFT          21
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0x00000003

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x00008000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             15
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_SHIFT        14
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_SHIFT         1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_VCXO1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_VCXO2_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT             0x00000040

/***************************************************************************
 *PLL_VCXO2_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_VCXO2_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_SHIFT         16

/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00005005

/***************************************************************************
 *PLL_VCXO2_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_MASK               0x20000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_SHIFT              29
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_SHIFT          21
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT            0x00000003

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK              0x00008000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT             15
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_SHIFT        14
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_SHIFT         1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_VCXO2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000f

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000008

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000008

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT                   0x00000002

/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT               0x00000078

/***************************************************************************
 *PLL_XPT_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_XPT_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_XPT_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_XPT_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002

/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000003

/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_XPT_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_XPT_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT              1

/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT                 0
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT               0x00000000

/***************************************************************************
 *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
 ***************************************************************************/
/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_ADC_4P5_CLOCK [00:00] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_ADC_4P5_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_ADC_4P5_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_ADC_4P5_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
 ***************************************************************************/
/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *APM_CHIP_TOP_INST_CLOCK_DISABLE - Disable APM_CHIP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE :: DISABLE_APM_200_SCAN_CLOCK [02:02] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_200_SCAN_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_200_SCAN_CLOCK_SHIFT 2
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_200_SCAN_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE :: DISABLE_APM_200_BYPASS_CLOCK [01:01] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_200_BYPASS_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_200_BYPASS_CLOCK_SHIFT 1
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_200_BYPASS_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE :: DISABLE_APM_100_BYPASS_CLOCK [00:00] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_100_BYPASS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_100_BYPASS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_DISABLE_APM_100_BYPASS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_APM_200_SCAN_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_200_SCAN_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_200_SCAN_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_APM_200_BYPASS_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_200_BYPASS_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_200_BYPASS_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_APM_100_BYPASS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_100_BYPASS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_100_BYPASS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *APM_CHIP_TOP_INST_CLOCK_ENABLE - Apm chip top inst clock enable
 ***************************************************************************/
/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE :: APM_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS :: APM_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  3

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVN_M_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVN_M_BVB_324_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_BVB_324_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_BVB_324_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVN_M_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVN_M_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_M_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVN_M_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVN_M_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_M_BVB_324_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVN_M_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVN_M_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_M_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVN_M_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVN_M_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      4

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_324_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_324_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           1

/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT    1

/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable
 ***************************************************************************/
/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffe0
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT       5

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_TP_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_SCB_450_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_SCB_450_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_SCB_450_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_SCB_450_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CLKGEN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_TP_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_TP_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_TP_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_SCB_450_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_SCB_450_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_SCB_450_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CLKGEN_INST_CLOCK_SELECT - Clkgen inst clock select
 ***************************************************************************/
/* CLKGEN :: CLKGEN_INST_CLOCK_SELECT :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_SELECT_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_SELECT_reserved0_SHIFT       1

/* CLKGEN :: CLKGEN_INST_CLOCK_SELECT :: CG_SCB_CLOCK_SELECT [00:00] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_SELECT_CG_SCB_CLOCK_SELECT_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_SELECT_CG_SCB_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_SELECT_CG_SCB_CLOCK_SELECT_DEFAULT 0x00000001

/***************************************************************************
 *CLOCK_MONITOR_CONTROL - Clock Monitor Control
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001

/***************************************************************************
 *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff

/***************************************************************************
 *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1

/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0

/***************************************************************************
 *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CORE_XPT_HIF_INST_CLOCK_DISABLE - Disable CORE_XPT_HIF_INST's clocks
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: reserved0 [31:09] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 9

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_XPT_324_SYS_CLOCK [08:08] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_324_SYS_CLOCK_MASK 0x00000100
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_324_SYS_CLOCK_SHIFT 8
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_324_SYS_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_XPT_150_TX1_CLOCK [07:07] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX1_CLOCK_MASK 0x00000080
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX1_CLOCK_SHIFT 7
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_XPT_150_TX0_CLOCK [06:06] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX0_CLOCK_MASK 0x00000040
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX0_CLOCK_SHIFT 6
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX0_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [05:05] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 5
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [03:03] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 3
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [02:02] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:09] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 9

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_324_SYS_CLOCK_STATUS [08:08] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_324_SYS_CLOCK_STATUS_MASK 0x00000100
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_324_SYS_CLOCK_STATUS_SHIFT 8

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_150_TX1_CLOCK_STATUS [07:07] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX1_CLOCK_STATUS_MASK 0x00000080
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX1_CLOCK_STATUS_SHIFT 7

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_150_TX0_CLOCK_STATUS [06:06] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX0_CLOCK_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX0_CLOCK_STATUS_SHIFT 6

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [05:05] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 5

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_EBI_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CORE_XPT_HIF_INST_CLOCK_ENABLE - Core xpt hif inst clock enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_reserved0_MASK  0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT 5

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_HIF_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_HIF_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_HIF_54_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_54_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_54_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_HIF_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_HIF_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_HIF_54_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CORE_XPT_HIF_INST_OBSERVE_CLOCK - Core xpt hif inst observe clock
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT 12

/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [11:11] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 11
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [09:06] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 6
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE - Disable CPU4355_BCM_MIPS_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: DISABLE_MIPS_MCLK_CLOCK [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_MIPS_MCLK_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE - Cpu4355 bcm mips top inst clock enable
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_DISABLE - Disable D3DSMAC_X4_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: DISABLE_DSMAC_MAC_CLOCK [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMAC_MAC_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_ENABLE - D3dsmac x4 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: DSMAC_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: DSMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_DISABLE - Disable DECT_UBUS_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: DISABLE_DECT_DEV_200_CLOCK [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_200_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_200_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_200_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DECT_DEV_200_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_200_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_200_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_ENABLE - Dect ubus top inst clock enable
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: DECT_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: DECT_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DISABLE_AVS_TOP_DURING_S2 - Disable AVS_TOP 54MHz clocks during S2 standby.
 ***************************************************************************/
/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT      1

/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000

/***************************************************************************
 *DISABLE_AVS_TOP_DURING_S2_SECURE - Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby.
 ***************************************************************************/
/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1

/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP_SECURE [00:00] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_MASK 0x00000001
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_SHIFT 0
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK  0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT 10

/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS0_CHANNEL5_FREQ_DISABLE_RDB_MACRO [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL5_FREQ_DISABLE_RDB_MACRO_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL5_FREQ_DISABLE_RDB_MACRO_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL5_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS0_CHANNEL4_FREQ_DISABLE_RDB_MACRO [08:08] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL4_FREQ_DISABLE_RDB_MACRO_MASK 0x00000100
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL4_FREQ_DISABLE_RDB_MACRO_SHIFT 8
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL4_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS0_CHANNEL3_FREQ_DISABLE_RDB_MACRO [07:07] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000080
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 7
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_DOCSIS_PLL_SYS0_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: CHANNEL5_FREQ [06:05] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL5_FREQ_MASK 0x00000060
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL5_FREQ_SHIFT 5
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL5_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: CHANNEL4_FREQ [04:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL4_FREQ_MASK 0x0000001c
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL4_FREQ_SHIFT 2
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL4_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_RDB_MACRO_CTRL :: CHANNEL3_FREQ [01:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK 0x00000003
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: reserved0 [31:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_reserved0_MASK  0xffffe000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_reserved0_SHIFT 13

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL5_FREQ_DISABLE_RDB_MACRO [12:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL5_FREQ_DISABLE_RDB_MACRO_MASK 0x00001000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL5_FREQ_DISABLE_RDB_MACRO_SHIFT 12
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL5_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO [11:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_MASK 0x00000800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_SHIFT 11
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL5_FREQ [08:07] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL5_FREQ_MASK 0x00000180
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL5_FREQ_SHIFT 7
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL5_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL4_FREQ [06:04] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_MASK 0x00000070
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_SHIFT 4
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL3_FREQ [03:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK 0x0000000c
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT 2
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL1_FREQ [01:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK 0x00000003
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_RESET_STATUS - DOCSIS_PLL_SYS2 Reset Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPA_INST_CLOCK_DISABLE - Disable DS_TOPA_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DS_TOPA_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_reserved0_SHIFT     1

/* CLKGEN :: DS_TOPA_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [00:00] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DS_TOPA_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPA_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPA_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPA_INST_CLOCK_ENABLE - Ds topa inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: DSA_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: DSA_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPB_INST_CLOCK_DISABLE - Disable DS_TOPB_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DS_TOPB_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_reserved0_SHIFT     1

/* CLKGEN :: DS_TOPB_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [00:00] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DS_TOPB_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPB_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPB_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPB_INST_CLOCK_ENABLE - Ds topb inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE :: DSB_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE_STATUS :: DSB_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_DSB_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_DSB_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPC_INST_CLOCK_DISABLE - Disable DS_TOPC_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DS_TOPC_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_reserved0_SHIFT     1

/* CLKGEN :: DS_TOPC_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [00:00] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DS_TOPC_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPC_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPC_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPC_INST_CLOCK_ENABLE - Ds topc inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_reserved0_SHIFT      2

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: DSC_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: DSC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPC_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: DSC_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: DSC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPD_INST_CLOCK_DISABLE - Disable DS_TOPD_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DS_TOPD_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_reserved0_SHIFT     1

/* CLKGEN :: DS_TOPD_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [00:00] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DS_TOPD_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPD_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPD_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPD_INST_CLOCK_ENABLE - Ds topd inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE :: DSC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPD_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE_STATUS :: DSC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_WFE_TOP_INST_CLOCK_DISABLE - Disable DS_WFE_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT  1

/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [00:00] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DS_WFE_TOP_INST_CLOCK_ENABLE - Ds wfe top inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT   1

/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE :: WFE_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS :: WFE_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_WFE_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_WFE_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_DISABLE - Disable DTP_DFAP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_324_CLOCK [02:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_SHIFT 2
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_216_CLOCK [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_SHIFT 1
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_324_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_216_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_ENABLE - Dtp dfap top inst clock enable
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xfffffff8
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffff8
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT      3

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_PHY600_CLOCK [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_PHY600_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_PHY600_CLOCK_SHIFT 2
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_PHY600_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_PHY371P25_CLOCK [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_PHY371P25_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_PHY371P25_CLOCK_SHIFT 1
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_PHY371P25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_PHY600_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_PHY600_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_PHY600_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_PHY371P25_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_PHY371P25_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_PHY371P25_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       4

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_RBUS_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_RBUS_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_RBUS_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_RBUS_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_BVB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_RBUS_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_RBUS_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_RBUS_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_BVB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1

/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       4

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_BVB_648_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_648_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_648_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_648_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_BVB_324_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_324_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_324_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_BVB_648_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_648_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_648_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_BVB_324_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *EAGLET_TOP_INST_CLOCK_DISABLE - Disable EAGLET_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT  1

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *EAGLET_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *EAGLET_TOP_INST_CLOCK_ENABLE - Eaglet top inst clock enable
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_MASK    0xfffffff8
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT   3

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: A15C_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: A15C_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: A15C_CPU_C_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *EAGLET_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: A15C_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: A15C_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: A15C_CPU_C_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *EAGLET_TOP_INST_ENABLE - Eaglet top inst enable
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_INST_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_reserved0_SHIFT         1

/* CLKGEN :: EAGLET_TOP_INST_ENABLE :: A15C_CPU_ENABLE [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_A15C_CPU_ENABLE_MASK    0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_A15C_CPU_ENABLE_SHIFT   0
#define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_A15C_CPU_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT - Egphy28 4port 33v 90o fc inst clock select
 ***************************************************************************/
/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: reserved0 [31:05] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_SHIFT 5

/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_REFCLK_CLOCK_SELECT [04:03] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_REFCLK_CLOCK_SELECT_MASK 0x00000018
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_REFCLK_CLOCK_SELECT_SHIFT 3
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_REFCLK_CLOCK_SELECT_DEFAULT 0x00000000

/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_BYPASS_CLOCK_SELECT [02:02] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_BYPASS_CLOCK_SELECT_MASK 0x00000004
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_BYPASS_CLOCK_SELECT_SHIFT 2
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_BYPASS_CLOCK_SELECT_DEFAULT 0x00000000

/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_25_54_CLOCK_SELECT [01:00] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_54_CLOCK_SELECT_MASK 0x00000003
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_54_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_54_CLOCK_SELECT_DEFAULT 0x00000000

/***************************************************************************
 *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE - G2u u2u ubus mod ss inst clock enable
 ***************************************************************************/
/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_DISABLE - Disable GFAP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff8
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    3

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_GFAP_324_CLOCK [02:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_SHIFT 2
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_GFAP_25_CLOCK [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_SHIFT 1
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_GFAP_324_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_324_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_324_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_GFAP_25_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_25_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_25_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE - Gfap top inst clock enable
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: GFAP_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: GFAP_324_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE0 - Gfap top inst clock enable0
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_reserved0_SHIFT    2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: GFAP_SCB_CLOCK_ENABLE0 [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_SHIFT 1
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: GFAP_M2MC0_GISB_CLOCK_ENABLE0 [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_SHIFT 0
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_DEFAULT 0x00000001

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: GFAP_SCB_CLOCK_ENABLE0_STATUS [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_SCB_CLOCK_ENABLE0_STATUS_SHIFT 1

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS_SHIFT 0

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: GFAP_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: GFAP_324_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_324_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_324_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *HVD0_TOP_INST_CLOCK_ENABLE - Hvd0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffff80
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     7

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_SCB_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_GISB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_CPU_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_CORE_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_BVB_324_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_BVB_324_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_BVB_324_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *HVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 7

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_SCB_CLOCK_ENABLE_STATUS [06:06] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 6

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_GISB_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_GISB_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_CPU_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_CORE_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_BVB_324_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *HVD0_TOP_INST_OBSERVE_CLOCK - Hvd0 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *HVD_SID1_TOP_INST_CLOCK_ENABLE - Hvd sid1 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xffffff80
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 7

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_SCB_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_SCB_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_SCB_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_GISB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_GISB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_GISB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_CPU_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_CPU_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_CPU_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_CORE_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_CORE_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_CORE_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_BVB_324_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_BVB_324_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_BVB_324_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD_SID1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD_SID1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *HVD_SID1_TOP_INST_CLOCK_ENABLE_SID - Hvd sid1 top inst clock enable sid
 ***************************************************************************/
/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: SID_CORE_CLOCK_ENABLE_SID [00:00] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_MASK 0x00000001
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_SHIFT 0
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_DEFAULT 0x00000001

/***************************************************************************
 *HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: SID_CORE_CLOCK_ENABLE_SID_STATUS [00:00] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_SHIFT 0

/***************************************************************************
 *HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 7

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_SCB_CLOCK_ENABLE_STATUS [06:06] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_SCB_CLOCK_ENABLE_STATUS_SHIFT 6

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_GISB_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_GISB_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_CPU_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_CPU_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_CORE_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_CORE_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_BVB_324_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD_SID1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD_SID1_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *HVD_SID1_TOP_INST_OBSERVE_CLOCK - Hvd sid1 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: HVD_SID1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: HVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: HVD_SID1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD_SID1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
 ***************************************************************************/
/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:08] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffff00
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            8

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [07:06] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x000000c0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 6
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [05:04] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000030
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [03:02] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x0000000c
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_TP_CLOCK [01:01] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_MASK   0x00000002
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_SHIFT  1
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_BPCM_CLOCK [00:00] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
 ***************************************************************************/
/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK             0xfffffff8
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT            3

/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [02:01] */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK    0x00000006
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT   1
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_DISABLE - Disable LEAP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    5

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_27_UART_CLOCK [04:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_SHIFT 4
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_216_CLOCK [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_SHIFT 3
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 2
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 1
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_UART_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_216_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_ENABLE - Leap top inst clock enable
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_54_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_54_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_54_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *LEAP_TOP_INST_OBSERVE_CLOCK - Leap top inst observe clock
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE - Memsys 32 wrapper 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_reserved0_SHIFT 4

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK - Memsys 32 wrapper 0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_STATUS - Memsys 32 wrapper 0 inst status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_STATUS :: MEMSYS0_PLL_LOCKED_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE - Memsys 32 wrapper 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_reserved0_SHIFT 4

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK - Memsys 32 wrapper 1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_STATUS - Memsys 32 wrapper 1 inst status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_STATUS :: MEMSYS1_PLL_LOCKED_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_SHIFT 0

/***************************************************************************
 *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
 ***************************************************************************/
/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  3

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
 ***************************************************************************/
/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
 ***************************************************************************/
/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  2

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
 ***************************************************************************/
/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MULTI_CLOCK_DISABLE - Disable MULTI's clocks
 ***************************************************************************/
/* CLKGEN :: MULTI_CLOCK_DISABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_MASK             0xffffff80
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_SHIFT            7

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_US_54_CLOCK [06:06] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_MASK   0x00000040
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_SHIFT  6
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK [05:05] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_CLOCK [04:04] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_TP_CLOCK [03:03] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_SHIFT 3
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_SMISB_CLOCK [02:02] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_SHIFT 2
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK [01:01] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK_SHIFT 1
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_BPCM_CLOCK [00:00] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MULTI_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_MASK      0xffffff80
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_SHIFT     7

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_US_54_CLOCK_STATUS [06:06] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_US_54_CLOCK_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_US_54_CLOCK_STATUS_SHIFT 6

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS [05:05] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_SHIFT 5

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_DI_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PAD_CLK_OUT0_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_MASK        0xfffffe00
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_SHIFT       9

/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLK_OUT1_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_MASK        0xfffffe00
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_SHIFT       9

/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLOCK_DISABLE - Disable PAD's clocks
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              2

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PAD_MUX_SELECT - Mux selects for Pad clocks
 ***************************************************************************/
/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:06] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xffffffc0
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 6

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [05:05] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK        0x00000020
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT       5
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT     0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT1_CLOCK [04:04] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK  0x00000010
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 4
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT0_CLOCK [03:03] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK  0x00000008
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 3
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK [02:02] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK_SHIFT 2
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_DISABLE - Disable PCIE_X2_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_RCBYPREF_100__CLOCK [01:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_RCBYPREF_100__CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_RCBYPREF_100__CLOCK_SHIFT 1
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_RCBYPREF_100__CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_RCBYPREF_100__CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_RCBYPREF_100__CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_RCBYPREF_100__CLOCK_STATUS_SHIFT 1

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_ENABLE - Pcie x2 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  4

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *PCIE_X2_TOP_INST_OBSERVE_CLOCK - Pcie x2 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT         4

/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000

/***************************************************************************
 *PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST - PLL_CPU_CORE Glitchless Clock Switching
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9

/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f

/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS - PLL_CPU_CORE Glitchless Switching
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4

/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0

/***************************************************************************
 *PLL_CPU_CORE_PLL_RESET_STATUS - PLL_CPU_CORE Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_SHIFT  2

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_CPU_CORE_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_reserved0_MASK     0xfffffff0
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_reserved0_SHIFT    4

/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_MASK       0x00000007
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_SHIFT      0
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_DEFAULT    0x00000000

/***************************************************************************
 *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_LC_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_reserved0_MASK           0xfffffffc
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_reserved0_SHIFT          2

/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO [01:01] */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000002
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 1
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: CHANNEL0_FREQ [00:00] */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK       0x00000001
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT      0
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT    0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xfffffc00
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        10

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL4_FREQ_DISABLE_RDB_MACRO [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL4_FREQ_DISABLE_RDB_MACRO_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL4_FREQ_DISABLE_RDB_MACRO_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL4_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO [08:08] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000100
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 8
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO [07:07] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000080
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 7
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO [06:06] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000040
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 6
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL4_FREQ [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL4_FREQ_MASK     0x00000020
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL4_FREQ_SHIFT    5
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL4_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL3_FREQ [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK     0x00000010
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT    4
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL1_FREQ [03:02] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK     0x0000000c
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT    2
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL0_FREQ [01:00] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK     0x00000003
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT  0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4

/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT         5

/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000

/***************************************************************************
 *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT         5

/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000

/***************************************************************************
 *PLL_STRAP_OVERRIDE - Disable
 ***************************************************************************/
/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2

/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK   0x00000002
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT  1
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_RESET_STATUS - PLL_SWITCH Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT        3

/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO [02:02] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000004
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 2
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: CHANNEL1_FREQ [01:00] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK     0x00000003
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_VCXO2_PLL_RESET_STATUS - PLL_VCXO2 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_XPT_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_SHIFT         5

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: CHANNEL1_FREQ [02:02] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK      0x00000004
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT     2
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: CHANNEL0_FREQ [01:00] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK      0x00000003
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT     0
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT   0x00000000

/***************************************************************************
 *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT       1

/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT_HIF [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_HIF_MASK 0x00000001
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_HIF_SHIFT 0
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_HIF_DEFAULT 0x00000000

/***************************************************************************
 *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
 ***************************************************************************/
/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:07] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xffffff80
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               7

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU [06:06] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_MASK                  0x00000040
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_SHIFT                 6
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_DEFAULT               0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [05:05] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK              0x00000020
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT             5
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT           0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [04:04] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK              0x00000010
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT             4
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT           0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [03:03] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK                  0x00000008
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT                 3
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT               0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [02:02] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000004
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                2
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS1 [01:01] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_MASK          0x00000002
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_SHIFT         1
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_DEFAULT       0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS0 [00:00] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_MASK          0x00000001
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_SHIFT         0
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_DEFAULT       0x00000000

/***************************************************************************
 *PM_PLL_LDO_POWERUP - Power management LDO PLL
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:12] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             12

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC1 [11:11] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_MASK      0x00000800
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_SHIFT     11
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_DEFAULT   0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC0 [10:10] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_MASK      0x00000400
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_SHIFT     10
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_DEFAULT   0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO2 [09:09] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_MASK    0x00000200
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_SHIFT   9
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_DEFAULT 0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO1 [08:08] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_MASK    0x00000100
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_SHIFT   8
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_DEFAULT 0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO0 [07:07] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_MASK    0x00000080
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_SHIFT   7
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_DEFAULT 0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SWITCH [06:06] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_MASK   0x00000040
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_SHIFT  6
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_DEFAULT 0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [05:05] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000020
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   5
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [04:04] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000010
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    4
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_LC [03:03] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_MASK       0x00000008
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_SHIFT      3
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_DEFAULT    0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_CPU_CORE [02:02] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_CORE_MASK 0x00000004
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_CORE_SHIFT 2
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_CORE_DEFAULT 0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [01:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000002
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   0x00000000

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_DOCSIS_PLL_SYS2 [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_MASK 0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_SHIFT 0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_DEFAULT 0x00000000

/***************************************************************************
 *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT    2

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_DSP_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_DSP_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_OBSERVE_CLOCK [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE - Raaga dsp top 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_DSP_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_DSP_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK - Raaga dsp top 1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_OBSERVE_CLOCK [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT     6

/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_0_INST_CLOCK_DISABLE - Disable SATA3_TOP_0_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_DISABLE :: DISABLE_SATA0_AT_SPEED_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_DISABLE_SATA0_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_DISABLE_SATA0_AT_SPEED_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_DISABLE_SATA0_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA0_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA0_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA0_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *SATA3_TOP_0_INST_CLOCK_ENABLE - Sata3 top 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT  3

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE :: SATA0_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE :: SATA0_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE :: SATA0_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_SATA0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS :: SATA0_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_SATA0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_SATA0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS :: SATA0_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_SATA0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_SATA0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS :: SATA0_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_SATA0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_ENABLE_STATUS_SATA0_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SATA3_TOP_0_INST_CLOCK_SELECT - Sata3 top 0 inst clock select
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_SELECT_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_SELECT_reserved0_SHIFT  3

/* CLKGEN :: SATA3_TOP_0_INST_CLOCK_SELECT :: SATA0_REF_CLOCK_SELECT [02:00] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_SELECT_SATA0_REF_CLOCK_SELECT_MASK 0x00000007
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_SELECT_SATA0_REF_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_0_INST_CLOCK_SELECT_SATA0_REF_CLOCK_SELECT_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_0_INST_OBSERVE_CLOCK - Sata3 top 0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: SATA3_TOP_0_INST_OBSERVE_CLOCK :: SATA0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SATA3_TOP_0_INST_OBSERVE_CLOCK :: SATA0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SATA3_TOP_0_INST_OBSERVE_CLOCK :: SATA0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_0_INST_OBSERVE_CLOCK_SATA0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_1_INST_CLOCK_DISABLE - Disable SATA3_TOP_1_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_DISABLE :: DISABLE_SATA1_AT_SPEED_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_DISABLE_SATA1_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_DISABLE_SATA1_AT_SPEED_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_DISABLE_SATA1_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA1_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA1_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA1_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *SATA3_TOP_1_INST_CLOCK_ENABLE - Sata3 top 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT  3

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE :: SATA1_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE :: SATA1_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE :: SATA1_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_SATA1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS :: SATA1_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_SATA1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_SATA1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS :: SATA1_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_SATA1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_SATA1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS :: SATA1_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_SATA1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_ENABLE_STATUS_SATA1_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SATA3_TOP_1_INST_CLOCK_SELECT - Sata3 top 1 inst clock select
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_SELECT_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_SELECT_reserved0_SHIFT  3

/* CLKGEN :: SATA3_TOP_1_INST_CLOCK_SELECT :: SATA1_REF_CLOCK_SELECT [02:00] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_SELECT_SATA1_REF_CLOCK_SELECT_MASK 0x00000007
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_SELECT_SATA1_REF_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_1_INST_CLOCK_SELECT_SATA1_REF_CLOCK_SELECT_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_1_INST_OBSERVE_CLOCK - Sata3 top 1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: SATA3_TOP_1_INST_OBSERVE_CLOCK :: SATA1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SATA3_TOP_1_INST_OBSERVE_CLOCK :: SATA1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SATA3_TOP_1_INST_OBSERVE_CLOCK :: SATA1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_1_INST_OBSERVE_CLOCK_SATA1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
 ***************************************************************************/
/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           2

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x00000002
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           1
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x00000001
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000

/***************************************************************************
 *SPARE - Spares
 ***************************************************************************/
/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000

/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_DISABLE - Disable SWITCH_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT  3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_TX_125_CLOCK [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_TX_125_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_TX_125_CLOCK_SHIFT 2
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_TX_125_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_25_CLOCK [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_200_CLOCK [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_TX_125_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_TX_125_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_TX_125_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_25_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_200_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_ENABLE - Switch top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_MASK    0xfffffff8
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT   3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SW_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SW_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SW_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SW_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SW_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SW_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SWITCH_TOP_INST_OBSERVE_CLOCK - Switch top inst observe clock
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_MASK   0xffffffc0
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT  6

/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SW_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SW_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SW_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff8
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    3

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [02:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 2
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *TESTPORT - Special Testport Controls
 ***************************************************************************/
/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4

/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE - Disable UBUS_MOD_PERIPH_FPM_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_SHIFT 7

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_27_CLOCK [06:06] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_MASK 0x00000040
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_SHIFT 6
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_XTAL_CLOCK [05:05] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_SHIFT 5
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_SPIM_100_CLOCK [04:04] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_SHIFT 4
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_HSPI_CLOCK [03:03] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_SHIFT 3
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_DEV_216_CLOCK [02:02] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_SHIFT 2
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_FPM_DEV_216_CLOCK [01:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 7

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_27_CLOCK_STATUS [06:06] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_SHIFT 6

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_XTAL_CLOCK_STATUS [05:05] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_XTAL_CLOCK_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_XTAL_CLOCK_STATUS_SHIFT 5

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_SPIM_100_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_HSPI_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_DEV_216_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_FPM_DEV_216_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE - Ubus mod periph fpm inst clock enable
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_ROUTER_1_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE - Unimac mbdma top router 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: UNIMAC_H2_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: UNIMAC_H2_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H2_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_ROUTER_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE - Unimac mbdma top router inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: UNIMAC_H1_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: UNIMAC_H1_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H1_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_STB_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE - Unimac mbdma top stb inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: UNIMAC_H_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: UNIMAC_H_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE - Unimac mbdma top wan inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_DISABLE - Disable USB0_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    2

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_27_MDIO_CLOCK [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_27_MDIO_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_27_MDIO_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_27_MDIO_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USB0_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_27_MDIO_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_27_MDIO_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_27_MDIO_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE - Disable USMAC_TC8X_DAVIC_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_TX_CLOCK [02:02] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_SHIFT 2
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_RX_CLOCK [01:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_216_CLOCK [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_TX_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_TX_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_TX_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_RX_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_RX_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_RX_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_216_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_216_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_216_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE - Usmac tc8x davic top inst clock enable
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE :: USMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: USMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *US_TOP_INST_CLOCK_ENABLE - Us top inst clock enable
 ***************************************************************************/
/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1

/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: US_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *US_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: US_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE - Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_USM_54_CLOCK [03:03] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_SHIFT 3
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_278_CLOCK [02:02] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_SHIFT 2
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_25_CLOCK [01:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_USM_54_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_278_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_25_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE - Utp crypto segdma top inst clock enable
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: UTP_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: UTP_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      4

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_GFX_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE - Vec aio gfx top inst clock enable
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE :: VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO - Vec aio gfx top inst clock enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0 - Vec aio gfx top inst clock enable m2mc0
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0 :: reserved0 [31:03] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_reserved0_SHIFT 3

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0 [02:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0 [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_CLOCK_ENABLE_M2MC0 [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_SHIFT 3

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_STATUS [02:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1 - Vec aio gfx top inst clock enable m2mc1
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:03] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 3

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1 [02:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1 [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_CLOCK_ENABLE_M2MC1 [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 3

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_STATUS [02:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_SYSTEMPORT_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT - Vec aio gfx top inst clock enable systemport
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT :: SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT :: SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS :: SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS_SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS_SYSTEMPORT_SCB_CLOCK_ENABLE_SYSTEMPORT_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS :: SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS_SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_SYSTEMPORT_STATUS_SYSTEMPORT_GISB_CLOCK_ENABLE_SYSTEMPORT_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC - Vec aio gfx top inst clock enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:07] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 7

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [06:06] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000040
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 6
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: VEC_GISB_CLOCK_ENABLE_VEC [05:05] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_648_CLOCK_ENABLE_VEC [04:04] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_648_CLOCK_ENABLE_VEC_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_648_CLOCK_ENABLE_VEC_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_648_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_324_CLOCK_ENABLE_VEC [03:03] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_SHIFT 3
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_324_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_216_CLOCK_ENABLE_VEC [02:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_216_CLOCK_ENABLE_VEC_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_216_CLOCK_ENABLE_VEC_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC :: QDAC_GISB_CLOCK_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF - Vec aio gfx top inst clock enable vec qdac intf
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 7

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [06:06] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 6

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_STATUS [05:05] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 5

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_648_CLOCK_ENABLE_VEC_STATUS [04:04] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_648_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_648_CLOCK_ENABLE_VEC_STATUS_SHIFT 4

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS [03:03] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_324_CLOCK_ENABLE_VEC_STATUS_SHIFT 3

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_216_CLOCK_ENABLE_VEC_STATUS [02:02] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 2

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: QDAC_GISB_CLOCK_ENABLE_VEC_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK - Vec aio gfx top inst observe clock
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:18] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffc0000
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 18

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [17:17] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00020000
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 17
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK [16:16] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00010000
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 16
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: VEC_CONTROL_OBSERVE_CLOCK [15:12] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_MASK 0x0000f000
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_SHIFT 12
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [11:11] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 11
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [09:06] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 6
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_GFX_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *VICE2_0_INST_CLOCK_ENABLE - Vice2 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_SHIFT      6

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_SCB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_CORE_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_BVB_216_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_216_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_216_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *VICE2_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_SCB_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_CORE_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_BVB_216_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_216_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_216_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *VICE2_1_INST_CLOCK_ENABLE - Vice2 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_MASK       0xffffff80
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_SHIFT      7

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_SCB_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_GISB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_CORE_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_BVB_324_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_324_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_324_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_BVB_216_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_216_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_216_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *VICE2_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffff80
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 7

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_SCB_CLOCK_ENABLE_STATUS [06:06] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_SHIFT 6

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_GISB_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_CORE_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_BVB_324_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_324_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_324_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_BVB_216_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_216_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_216_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *BSPI_CLOCK_SELECT - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3

/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK      0x00000006
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT     1
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT   0x00000000

/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *AVD_PLL_CTRL_WRAPPER_CONTROL - AVD_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: AVD_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT   2

/* CLKGEN :: AVD_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: AVD_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_AVD_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *MOCA_PLL_CTRL_WRAPPER_CONTROL - MOCA_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT  2

/* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *SWITCH_PLL_CTRL_WRAPPER_CONTROL - SWITCH_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: SWITCH_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2

/* CLKGEN :: SWITCH_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_SWITCH_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *RAAGA_PLL_CTRL_WRAPPER_CONTROL - RAAGA_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: RAAGA_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: RAAGA_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *VCXO0_PLL_CTRL_WRAPPER_CONTROL - VCXO0_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: VCXO0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2

/* CLKGEN :: VCXO0_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: VCXO0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_VCXO0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *VCXO1_PLL_CTRL_WRAPPER_CONTROL - VCXO1_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: VCXO1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2

/* CLKGEN :: VCXO1_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: VCXO1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_VCXO1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *VCXO2_PLL_CTRL_WRAPPER_CONTROL - VCXO2_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: VCXO2_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2

/* CLKGEN :: VCXO2_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: VCXO2_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_VCXO2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *LC_PLL_CTRL_WRAPPER_CONTROL - LC_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT    2

/* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *SC0_PLL_CTRL_WRAPPER_CONTROL - SC0_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT   2

/* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *SC1_PLL_CTRL_WRAPPER_CONTROL - SC1_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT   2

/* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000

/* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *SYS0_PLL_CTRL_WRAPPER_CONTROL - SYS0_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: SYS0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT  1

/* CLKGEN :: SYS0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_SYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *XPT_PLL_CTRL_WRAPPER_CONTROL - XPT_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: XPT_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT   1

/* CLKGEN :: XPT_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *CPU_PLL_CTRL_WRAPPER_CONTROL - CPU_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: CPU_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT   1

/* CLKGEN :: CPU_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL - DOCSISSYS0_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1

/* CLKGEN :: DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL - DOCSISSYS1_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1

/* CLKGEN :: DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL - DOCSISSYS2_PLL_CTRL_WRAPPER control
 ***************************************************************************/
/* CLKGEN :: DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1

/* CLKGEN :: DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */
#define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001
#define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0
#define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000

/***************************************************************************
 *CORE_XPT_HIF_BYP_CLOCK_SELECT - core_xpt_hif inst byp clock select
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_HIF_BYP_CLOCK_SELECT :: reserved0 [31:01] */
#define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_reserved0_SHIFT  1

/* CLKGEN :: CORE_XPT_HIF_BYP_CLOCK_SELECT :: BYP_CLOCK_PIN_SEL [00:00] */
#define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_BYP_CLOCK_PIN_SEL_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_BYP_CLOCK_PIN_SEL_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_BYP_CLOCK_PIN_SEL_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_SC1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

#endif /* #ifndef BCHP_CLKGEN_H__ */

/* End of File */