| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Sun Sep 14 03:14:46 2014 |
| * Full Compile MD5 Checksum ef22086ebd4065e4fea50dbc64f17e5e |
| * (minus title and desc) |
| * MD5 Checksum 39fcae49037a6337517df43bfc24b21f |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLKGEN_H__ |
| #define BCHP_CLKGEN_H__ |
| |
| /*************************************************************************** |
| *CLKGEN - clkgen registers |
| ***************************************************************************/ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON 0x20480000 /* Bandgap Power on */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x20480004 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x20480008 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x2048000c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x20480010 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x20480014 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x20480018 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV 0x2048001c /* Pre multiplier */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN 0x20480020 /* PLL GAIN */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL 0x20480024 /* Hold PLL all channels */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL 0x20480028 /* Ldo voltage control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON 0x2048002c /* LDO Power on */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS 0x20480030 /* Lock Status */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC 0x20480034 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2 0x20480038 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON 0x2048003c /* Poweron */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET 0x20480040 /* Resets */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x20480044 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x20480048 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS 0x2048004c /* Status */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON 0x20480050 /* Bandgap Power on */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x20480054 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x20480058 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x2048005c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x20480060 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV 0x20480064 /* Pre multiplier */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN 0x20480068 /* PLL GAIN */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL 0x2048006c /* Hold PLL all channels */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL 0x20480070 /* Ldo voltage control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON 0x20480074 /* LDO Power on */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS 0x20480078 /* Lock Status */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC 0x2048007c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2 0x20480080 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON 0x20480084 /* Poweron */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET 0x20480088 /* Resets */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x2048008c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x20480090 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS 0x20480094 /* Status */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON 0x20480098 /* Bandgap Power on */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 0x2048009c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 0x204800a0 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 0x204800a4 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 0x204800a8 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV 0x204800ac /* Pre multiplier */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN 0x204800b0 /* PLL GAIN */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL 0x204800b4 /* Hold PLL all channels */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL 0x204800b8 /* Ldo voltage control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON 0x204800bc /* LDO Power on */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS 0x204800c0 /* Lock Status */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC 0x204800c4 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2 0x204800c8 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON 0x204800cc /* Poweron */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET 0x204800d0 /* Resets */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH 0x204800d4 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW 0x204800d8 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS 0x204800dc /* Status */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 0x204800e0 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 0x204800e4 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV 0x204800e8 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC 0x204800ec /* Fractional */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN 0x204800f0 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON 0x204800f4 /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS 0x204800f8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC 0x204800fc /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2 0x20480100 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON 0x20480104 /* Poweron */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET 0x20480108 /* Resets */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH 0x2048010c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW 0x20480110 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS 0x20480114 /* Status */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x20480118 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x2048011c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x20480120 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3 0x20480124 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4 0x20480128 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CONTROL 0x2048012c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV 0x20480130 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN 0x20480134 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL 0x20480138 /* Hold PLL all channels */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL 0x2048013c /* Ldo voltage control */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON 0x20480140 /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS 0x20480144 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC 0x20480148 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2 0x2048014c /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL 0x20480150 /* selection of the output clock from the PLL core */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_PWRON 0x20480154 /* Poweron */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET 0x20480158 /* Resets */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_STATUS 0x2048015c /* Status */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST 0x20480160 /* enable and selection pf PLL test */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x20480164 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x20480168 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x2048016c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x20480170 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV 0x20480174 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN 0x20480178 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON 0x2048017c /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS 0x20480180 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC 0x20480184 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2 0x20480188 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON 0x2048018c /* Poweron */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET 0x20480190 /* Resets */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x20480194 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x20480198 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS 0x2048019c /* Status */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_BG_PWRON 0x204801a0 /* Bandgap Power on */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0 0x204801a4 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1 0x204801a8 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2 0x204801ac /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3 0x204801b0 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4 0x204801b4 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5 0x204801b8 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV 0x204801bc /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN 0x204801c0 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_HOLD_CH_ALL 0x204801c4 /* Hold PLL all channels */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_CTRL 0x204801c8 /* Ldo voltage control */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_PWRON 0x204801cc /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS 0x204801d0 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC 0x204801d4 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2 0x204801d8 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_PWRON 0x204801dc /* Poweron */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_RESET 0x204801e0 /* Resets */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH 0x204801e4 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW 0x204801e8 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_STATUS 0x204801ec /* Status */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x204801f0 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV 0x204801f4 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC 0x204801f8 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN 0x204801fc /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON 0x20480200 /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS 0x20480204 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC 0x20480208 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2 0x2048020c /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRON 0x20480210 /* Poweron */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET 0x20480214 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x20480218 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x2048021c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS 0x20480220 /* Status */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x20480224 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV 0x20480228 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC 0x2048022c /* Fractional */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN 0x20480230 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON 0x20480234 /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS 0x20480238 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC 0x2048023c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2 0x20480240 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRON 0x20480244 /* Poweron */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET 0x20480248 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x2048024c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x20480250 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS 0x20480254 /* Status */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x20480258 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x2048025c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x20480260 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x20480264 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5 0x20480268 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV 0x2048026c /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN 0x20480270 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON 0x20480274 /* LDO Power on */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS 0x20480278 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC 0x2048027c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2 0x20480280 /* Mscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRON 0x20480284 /* Poweron */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET 0x20480288 /* Resets */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x2048028c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x20480290 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS 0x20480294 /* Status */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE 0x20480298 /* Aif wb cab top inst clock enable */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS 0x2048029c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_SELECT 0x204802a0 /* Aif wb cab top inst clock select */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK 0x204802a4 /* Aif wb cab top inst observe clock */ |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x204802a8 /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */ |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x204802ac /* Clock Disable Status */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE 0x204802b0 /* Disable APM_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_STATUS 0x204802b4 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE 0x204802b8 /* Apm top inst clock enable */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_STATUS 0x204802bc /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE 0x204802c0 /* Disable CLKGEN's clocks */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS 0x204802c4 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE 0x204802c8 /* Clkgen inst clock enable */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS 0x204802cc /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x204802d0 /* Clock Monitor Control */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x204802d4 /* Clock Monitor Max Reference Count */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x204802d8 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x204802dc /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x204802e0 /* Clock Monitor View Counter */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE 0x204802e4 /* Cmd afec topa inst clock enable */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS 0x204802e8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK 0x204802ec /* Cmd afec topa inst observe clock */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE 0x204802f0 /* Cmd afec topb inst clock enable */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS 0x204802f4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK 0x204802f8 /* Cmd afec topb inst observe clock */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE 0x204802fc /* Disable CORE_XPT_HIF_INST's clocks */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS 0x20480300 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE 0x20480304 /* Core xpt hif inst clock enable */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS 0x20480308 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK 0x2048030c /* Core xpt hif inst observe clock */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE 0x20480310 /* Disable CPU4355_BCM_MIPS_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS 0x20480314 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE 0x20480318 /* Cpu4355 bcm mips top inst clock enable */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS 0x2048031c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK 0x20480320 /* Cpu4355 bcm mips top inst observe clock */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE 0x20480324 /* Disable D31DSMAC_OFDM_TOPA_INST's clocks */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS 0x20480328 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE 0x2048032c /* D31dsmac ofdm topa inst clock enable */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS 0x20480330 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE 0x20480334 /* Disable D31DSMAC_OFDM_TOPB_INST's clocks */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS 0x20480338 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE 0x2048033c /* D31dsmac ofdm topb inst clock enable */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS 0x20480340 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE 0x20480344 /* Disable D3DSMAC_32CH_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS 0x20480348 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE 0x2048034c /* D3dsmac 32ch top inst clock enable */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS 0x20480350 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE 0x20480354 /* Disable DECT_UBUS_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS 0x20480358 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE 0x2048035c /* Dect ubus top inst clock enable */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS 0x20480360 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2 0x20480364 /* Disable AVS_TOP 54MHz clocks during S2 standby. */ |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x20480368 /* Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS 0x2048036c /* DOCSIS_PLL_SYS2 Reset Status */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE 0x20480370 /* Ds topa inst clock enable */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS 0x20480374 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_CONTROL 0x20480378 /* Ds topa inst observe clock control */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE 0x2048037c /* Ds topa inst observe clock enable */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV 0x20480380 /* Ds topa inst observe clock enable div */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE 0x20480384 /* Disable DTP_DFAP_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x20480388 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE 0x2048038c /* Dtp dfap top inst clock enable */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480390 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE 0x20480394 /* Disable EAGLET_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS 0x20480398 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE 0x2048039c /* Eaglet top inst clock enable */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS 0x204803a0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE 0x204803a4 /* Eaglet top inst enable */ |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT 0x204803a8 /* Egphy28 4port 33v 90o fc inst clock select */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE 0x204803ac /* Disable G2U_U2U_UBUS_MOD_SS_INST's clocks */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS 0x204803b0 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE 0x204803b4 /* G2u u2u ubus mod ss inst clock enable */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS 0x204803b8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x204803bc /* Mux selects for Internal clocks */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE 0x204803c0 /* Disable LEAP_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS 0x204803c4 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE 0x204803c8 /* Leap top inst clock enable */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS 0x204803cc /* Clock Enable Status */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK 0x204803d0 /* Leap top inst observe clock */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE 0x204803d4 /* Disable MEMC0_DDR3_3390_TOP_WRAPPER_INST's clocks */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS 0x204803d8 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE 0x204803dc /* Memc0 ddr3 3390 top wrapper inst clock enable */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS 0x204803e0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK 0x204803e4 /* Memc0 ddr3 3390 top wrapper inst observe clock */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS 0x204803e8 /* Memc0 ddr3 3390 top wrapper inst status */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE 0x204803ec /* Disable MEMC1_DDR3_3390_TOP_WRAPPER_INST's clocks */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS 0x204803f0 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE 0x204803f4 /* Memc1 ddr3 3390 top wrapper inst clock enable */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS 0x204803f8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK 0x204803fc /* Memc1 ddr3 3390 top wrapper inst observe clock */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS 0x20480400 /* Memc1 ddr3 3390 top wrapper inst status */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE 0x20480404 /* Disable MOCAMAC_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS 0x20480408 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x2048040c /* Mocamac top inst clock enable */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x20480410 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x20480414 /* Mocamac top inst observe clock */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x20480418 /* Mocaphy top inst clock enable */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x2048041c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x20480420 /* Mocaphy top inst observe clock */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE 0x20480424 /* Disable MULTI's clocks */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS 0x20480428 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION 0x2048042c /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION 0x20480430 /* Select observation clk */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x20480434 /* Disable PAD's clocks */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS 0x20480438 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT 0x2048043c /* Mux selects for Pad clocks */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE 0x20480440 /* Disable PCIE_X2_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS 0x20480444 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE 0x20480448 /* Pcie x2 top inst clock enable */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS 0x2048044c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK 0x20480450 /* Pcie x2 top inst observe clock */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST 0x20480454 /* PLL_CPU_CORE Glitchless Clock Switching */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS 0x20480458 /* PLL_CPU_CORE Glitchless Switching */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS 0x2048045c /* PLL_CPU_CORE Reset Status */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS 0x20480460 /* PLL_LC Reset Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS 0x20480464 /* PLL_MOCA Reset Status */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS 0x20480468 /* PLL_SC0 Reset Status */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS 0x2048046c /* PLL_SC1 Reset Status */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE 0x20480470 /* Disable */ |
| #define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL 0x20480474 /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x20480478 /* PLL Alive in Standby Mode */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x2048047c /* Power management LDO PLL */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE 0x20480480 /* Disable PROD_OTP_INST's clocks */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x20480484 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE 0x20480488 /* Prod otp inst clock enable */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x2048048c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE 0x20480490 /* Disable RDP_TOP_WRAPPER_INST's clocks */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS 0x20480494 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE 0x20480498 /* Rdp top wrapper inst clock enable */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS 0x2048049c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE 0x204804a0 /* Sectop inst clock enable */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS 0x204804a4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x204804a8 /* Sectop inst observe clock */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x204804ac /* Mux selects for Smartcard clocks */ |
| #define BCHP_CLKGEN_SPARE 0x204804b0 /* Spares */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE 0x204804b4 /* Disable SWITCH_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS 0x204804b8 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE 0x204804bc /* Switch top inst clock enable */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS 0x204804c0 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK 0x204804c4 /* Switch top inst observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE 0x204804c8 /* Disable SYS_CTRL_INST's clocks */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x204804cc /* Clock Disable Status */ |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE 0x204804d0 /* Tcofdm top inst clock enable */ |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS 0x204804d4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE 0x204804d8 /* Disable TCQAM_DAVIC_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS 0x204804dc /* Clock Disable Status */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE 0x204804e0 /* Tcqam davic top inst clock enable */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS 0x204804e4 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_TESTPORT 0x204804e8 /* Special Testport Controls */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE 0x204804ec /* Disable UBUS_MOD_PERIPH_FPM_INST's clocks */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS 0x204804f0 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE 0x204804f4 /* Ubus mod periph fpm inst clock enable */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS 0x204804f8 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE 0x204804fc /* Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS 0x20480500 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE 0x20480504 /* Unimac mbdma top wan inst clock enable */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS 0x20480508 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE 0x2048050c /* Disable USB0_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS 0x20480510 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE 0x20480514 /* Usb0 top inst clock enable */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x20480518 /* Usb0 top inst clock enable ahb */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x2048051c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x20480520 /* Usb0 top inst clock enable axi */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x20480524 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x20480528 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK 0x2048052c /* Usb0 top inst observe clock */ |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE 0x20480530 /* Usmac top inst clock enable */ |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x20480534 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE 0x20480538 /* Us top inst clock enable */ |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS 0x2048053c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE 0x20480540 /* Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS 0x20480544 /* Clock Disable Status */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE 0x20480548 /* Utp crypto segdma top inst clock enable */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS 0x2048054c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE 0x20480550 /* Wod rcvr topa inst clock enable */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS 0x20480554 /* Clock Enable Status */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE 0x20480558 /* Wod rcvr topb inst clock enable */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS 0x2048055c /* Clock Enable Status */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT 0x20480560 /* PLL RDB Macro Disable */ |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL 0x20480564 /* MOCA_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL 0x20480568 /* LC_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL 0x2048056c /* SC0_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL 0x20480570 /* SC1_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL 0x20480574 /* XPT_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_RDP_PLL_CTRL_WRAPPER_CONTROL 0x20480578 /* RDP_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL 0x2048057c /* CPU_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL 0x20480580 /* DOCSISSYS0_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL 0x20480584 /* DOCSISSYS1_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL 0x20480588 /* DOCSISSYS2_PLL_CTRL_WRAPPER control */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT 0x2048058c /* CORE_XPT_HIF_BYP_CLOCK_SELECT control */ |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_BG_PWRON - Bandgap Power on |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000090 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000e |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000000e |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT 0x00000090 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT 31 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT 21 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x00180000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 19 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 15 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT 14 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS0_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_BG_PWRON - Bandgap Power on |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000024 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL - Hold PLL all channels |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_LDO_CTRL - Ldo voltage control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_LOW [31:31] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_SHIFT 31 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: REF_ALT_OFFS [21:21] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_SHIFT 21 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: PWM_RATE [20:19] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_MASK 0x00180000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT 19 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: POST_CTRL_RESETB [18:17] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: FAST_LOCK [15:15] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT 15 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DITHER_DISABLE [14:14] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_SHIFT 14 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: PLLRESERVED0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS1_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_BG_PWRON - Bandgap Power on |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000001c |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000001c |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_DEFAULT 0x0000007d |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL - Hold PLL all channels |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_LDO_CTRL - Ldo voltage control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_LOW [31:31] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_SHIFT 31 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: REF_ALT_OFFS [21:21] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_SHIFT 21 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: PWM_RATE [20:19] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_MASK 0x00180000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_SHIFT 19 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: POST_CTRL_RESETB [18:17] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_SHIFT 17 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: FAST_LOCK [15:15] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_SHIFT 15 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DITHER_DISABLE [14:14] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_SHIFT 14 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: PLLRESERVED0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_DEFAULT 0x000000a7 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_RANGE [31:30] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_FB_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PWM_RATE [21:20] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: POST_CTRL_RESETB [19:18] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED2 [17:16] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED1 [15:15] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: NDIV_RELOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: FAST_LOCK [13:13] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: PLLRESERVED0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: LDO [01:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000006c |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000002d |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000036 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000036 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000032 |
| |
| /* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK 0xffffff80 |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT 7 |
| |
| /* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078 |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_LDO_CTRL - Ldo voltage control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000003f |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT 31 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK 0x70000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK 0x007fff80 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT 7 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_OUTPUT [06:06] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_OUTPUT_MASK 0x00000040 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_OUTPUT_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_OUTPUT_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK 0x0000000c |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: VCO_POST_MUX_EN [31:31] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_VCO_POST_MUX_EN_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_VCO_POST_MUX_EN_SHIFT 31 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_VCO_POST_MUX_EN_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [30:30] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [29:29] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [28:28] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: REFD2C_BIAS [27:25] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_REFD2C_BIAS_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_REFD2C_BIAS_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_REFD2C_BIAS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [24:15] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK 0x01ff8000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: O_FREF_DISABLE [14:14] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_O_FREF_DISABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_O_FREF_DISABLE_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_O_FREF_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: KI_STARTLOW [13:13] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_KI_STARTLOW_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_KI_STARTLOW_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_KI_STARTLOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: KI_BOOST [12:12] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_KI_BOOST_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_KI_BOOST_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_KI_BOOST_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [11:10] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK 0x00000c00 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [09:09] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [08:08] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK 0x00000100 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT 8 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [07:07] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK 0x00000080 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT 7 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_50OHM [06:06] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_50OHM_MASK 0x00000040 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_50OHM_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_50OHM_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK 0x00000030 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK 0xffffffff |
| #define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_TEST - enable and selection pf PLL test |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000012 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT 0x000000c8 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC2 :: LDO [01:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_BG_PWRON - Bandgap Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_BG_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_BG_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_BG_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RDP_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000a |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000004 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000003c |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000a |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000b |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000000b |
| |
| /* CLKGEN :: PLL_RDP_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_RDP_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_RDP_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_DIV_NDIV_INT_DEFAULT 0x00000078 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_RDP_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007 |
| |
| /* CLKGEN :: PLL_RDP_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_HOLD_CH_ALL - Hold PLL all channels |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_HOLD_CH_ALL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_HOLD_CH_ALL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RDP_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_LDO_CTRL - Ldo voltage control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_LDO_CTRL :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_CTRL_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_CTRL_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_RDP_PLL_LDO_CTRL :: LDO_CTRL [15:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_CTRL_LDO_CTRL_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_CTRL_LDO_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_CTRL_LDO_CTRL_DEFAULT 0x00005005 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RDP_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RDP_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RDP_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: VCO_RANGE_LOW [31:31] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_RANGE_LOW_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_RANGE_LOW_SHIFT 31 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: VCO_RANGE_HIGH [30:30] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_RANGE_HIGH_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_RANGE_HIGH_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: VCO_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_VCO_DIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: REF_ALT_OFFS [21:21] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_REF_ALT_OFFS_MASK 0x00200000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_REF_ALT_OFFS_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_REF_ALT_OFFS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: PWM_RATE [20:19] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_PWM_RATE_MASK 0x00180000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_PWM_RATE_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_PWM_RATE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: POST_CTRL_RESETB [18:17] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_POST_CTRL_RESETB_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: NDIV_RELOCK [16:16] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_NDIV_RELOCK_MASK 0x00010000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_NDIV_RELOCK_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: FAST_LOCK [15:15] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_FAST_LOCK_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_FAST_LOCK_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: DITHER_DISABLE [14:14] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DITHER_DISABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DITHER_DISABLE_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00001ffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC :: AUX_CTRL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_AUX_CTRL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_AUX_CTRL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_MISC2 :: PLLRESERVED0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2_PLLRESERVED0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2_DIG_INPUT_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2_DIG_INPUT_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RDP_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RDP_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RDP_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_RDP_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_RDP_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_RDP_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RDP_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_RDP_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_RDP_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_RDP_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_RDP_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030 |
| |
| /* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT 0x00000030 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_MISC2 :: LDO [01:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030 |
| |
| /* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT 0x00000030 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_MISC2 :: LDO [01:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000f |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000008 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000003c |
| |
| /* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK 0x00003c00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK 0x000003ff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT 0x00000078 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK 0xfffffc00 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT 10 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_LDO_PWRON - LDO Power on |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT 0x00000002 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK 0x0e000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK 0x01000000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK 0x000c0000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK 0x00030000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT 16 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK 0x00008000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT 15 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK 0x00004000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT 13 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT 2 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_MISC2 :: LDO [01:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_MASK 0x00000003 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_PWRON - Poweron |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_XPT_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AIF_WB_CAB_TOP_INST_CLOCK_ENABLE - Aif wb cab top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_ENABLE :: AIF_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_AIF_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_AIF_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_AIF_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_ENABLE :: AIF_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_AIF_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_AIF_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_AIF_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS :: AIF_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS_AIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS_AIF_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS :: AIF_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS_AIF_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_ENABLE_STATUS_AIF_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *AIF_WB_CAB_TOP_INST_CLOCK_SELECT - Aif wb cab top inst clock select |
| ***************************************************************************/ |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_CLOCK_SELECT :: AIF_BYP_CLK_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_SELECT_AIF_BYP_CLK_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_SELECT_AIF_BYP_CLK_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_CLOCK_SELECT_AIF_BYP_CLK_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK - Aif wb cab top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: AIF_IN1_ENABLE_OBSERVE_CLOCK [11:11] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_ENABLE_OBSERVE_CLOCK_MASK 0x00000800 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_ENABLE_OBSERVE_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: AIF_IN1_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: AIF_IN1_CONTROL_OBSERVE_CLOCK [09:06] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_CONTROL_OBSERVE_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: AIF_IN0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: AIF_IN0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK :: AIF_IN0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_AIF_WB_CAB_TOP_INST_OBSERVE_CLOCK_AIF_IN0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *APM_TOP_INST_CLOCK_DISABLE - Disable APM_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: APM_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: APM_TOP_INST_CLOCK_DISABLE :: DISABLE_APM_XTAL_54_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_DISABLE_APM_XTAL_54_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_DISABLE_APM_XTAL_54_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_DISABLE_APM_XTAL_54_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *APM_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: APM_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: APM_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_APM_XTAL_54_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_XTAL_54_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_APM_XTAL_54_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *APM_TOP_INST_CLOCK_ENABLE - Apm top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: APM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: APM_TOP_INST_CLOCK_ENABLE :: APM_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *APM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: APM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: APM_TOP_INST_CLOCK_ENABLE_STATUS :: APM_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_APM_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_GISB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CLKGEN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_GISB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_CONTROL - Clock Monitor Control |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CMD_AFEC_TOPA_INST_CLOCK_ENABLE - Cmd afec topa inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_CLOCK_ENABLE :: AFEC_A_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_AFEC_A_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_AFEC_A_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_AFEC_A_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_CLOCK_ENABLE :: AFEC_A_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_AFEC_A_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_AFEC_A_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_AFEC_A_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS :: AFEC_A_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS_AFEC_A_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS_AFEC_A_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS :: AFEC_A_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS_AFEC_A_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_CLOCK_ENABLE_STATUS_AFEC_A_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CMD_AFEC_TOPA_INST_OBSERVE_CLOCK - Cmd afec topa inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_OBSERVE_CLOCK :: AFEC_B_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_OBSERVE_CLOCK :: AFEC_A_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_A_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_A_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_A_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CMD_AFEC_TOPA_INST_OBSERVE_CLOCK :: AFEC_A_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_A_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_A_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPA_INST_OBSERVE_CLOCK_AFEC_A_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CMD_AFEC_TOPB_INST_CLOCK_ENABLE - Cmd afec topb inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_CLOCK_ENABLE :: AFEC_B_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_AFEC_B_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_AFEC_B_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_AFEC_B_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_CLOCK_ENABLE :: AFEC_B_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_AFEC_B_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_AFEC_B_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_AFEC_B_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS :: AFEC_B_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS_AFEC_B_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS_AFEC_B_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS :: AFEC_B_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS_AFEC_B_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_CLOCK_ENABLE_STATUS_AFEC_B_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CMD_AFEC_TOPB_INST_OBSERVE_CLOCK - Cmd afec topb inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_OBSERVE_CLOCK :: AFEC_B_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_OBSERVE_CLOCK :: AFEC_B_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CMD_AFEC_TOPB_INST_OBSERVE_CLOCK :: AFEC_B_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CMD_AFEC_TOPB_INST_OBSERVE_CLOCK_AFEC_B_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_HIF_INST_CLOCK_DISABLE - Disable CORE_XPT_HIF_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_XPT_324_SYS_CLOCK [08:08] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_324_SYS_CLOCK_MASK 0x00000100 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_324_SYS_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_324_SYS_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_XPT_150_TX1_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX1_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX1_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_XPT_150_TX0_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX0_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX0_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_XPT_150_TX0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_324_SYS_CLOCK_STATUS [08:08] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_324_SYS_CLOCK_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_324_SYS_CLOCK_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_150_TX1_CLOCK_STATUS [07:07] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX1_CLOCK_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX1_CLOCK_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_150_TX0_CLOCK_STATUS [06:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX0_CLOCK_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_150_TX0_CLOCK_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_EBI_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_HIF_INST_CLOCK_ENABLE - Core xpt hif inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_MCP_CLOCK_ENABLE [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_MCP_CLOCK_ENABLE_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_MCP_CLOCK_ENABLE_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_MCP_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_HIF_SCB_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_SCB_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_SCB_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_HIF_GISB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_GISB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_GISB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_HIF_54_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_54_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_54_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_MCP_CLOCK_ENABLE_STATUS [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_MCP_CLOCK_ENABLE_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_MCP_CLOCK_ENABLE_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_HIF_SCB_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_SCB_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_HIF_GISB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_GISB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_HIF_54_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_HIF_INST_OBSERVE_CLOCK - Core xpt hif inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [11:11] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000800 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [09:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CORE_XPT_HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE - Disable CPU4355_BCM_MIPS_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: DISABLE_MIPS_MCLK_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_MIPS_MCLK_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE - Cpu4355 bcm mips top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK - Cpu4355 bcm mips top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE - Disable D31DSMAC_OFDM_TOPA_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE :: DISABLE_DSMACA_MAC_324_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_DISABLE_DSMACA_MAC_324_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_DISABLE_DSMACA_MAC_324_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_DISABLE_DSMACA_MAC_324_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMACA_MAC_324_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMACA_MAC_324_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMACA_MAC_324_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE - D31dsmac ofdm topa inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE :: DSMAC_A_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_DSMAC_A_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_DSMAC_A_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_DSMAC_A_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS :: DSMAC_A_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS_DSMAC_A_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPA_INST_CLOCK_ENABLE_STATUS_DSMAC_A_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE - Disable D31DSMAC_OFDM_TOPB_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE :: DISABLE_DSMACB_MAC_324_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_DISABLE_DSMACB_MAC_324_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_DISABLE_DSMACB_MAC_324_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_DISABLE_DSMACB_MAC_324_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMACB_MAC_324_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMACB_MAC_324_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMACB_MAC_324_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE - D31dsmac ofdm topb inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE :: DSMAC_B_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_DSMAC_B_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_DSMAC_B_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_DSMAC_B_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS :: DSMAC_B_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS_DSMAC_B_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_D31DSMAC_OFDM_TOPB_INST_CLOCK_ENABLE_STATUS_DSMAC_B_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE - Disable D3DSMAC_32CH_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE :: DISABLE_DSMAC_MAC_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMAC_MAC_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE - D3dsmac 32ch top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE :: DSMAC_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE :: DSMAC_MCP_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_MCP_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_MCP_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_MCP_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE :: DSMAC_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_MCP_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_MCP_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_MCP_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_D3DSMAC_32CH_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DECT_UBUS_TOP_INST_CLOCK_DISABLE - Disable DECT_UBUS_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: DISABLE_DECT_DEV_200_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_200_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_200_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_200_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DECT_DEV_200_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_200_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_200_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DECT_UBUS_TOP_INST_CLOCK_ENABLE - Dect ubus top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: DECT_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: DECT_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DISABLE_AVS_TOP_DURING_S2 - Disable AVS_TOP 54MHz clocks during S2 standby. |
| ***************************************************************************/ |
| /* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */ |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001 |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0 |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DISABLE_AVS_TOP_DURING_S2_SECURE - Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. |
| ***************************************************************************/ |
| /* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP_SECURE [00:00] */ |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_SHIFT 0 |
| #define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSIS_PLL_SYS2_PLL_RESET_STATUS - DOCSIS_PLL_SYS2 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DS_TOPA_INST_CLOCK_ENABLE - Ds topa inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: DSA_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: DSA_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DS_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: DSA_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: DSA_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DS_TOPA_INST_OBSERVE_CLOCK_CONTROL - Ds topa inst observe clock control |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_INST_OBSERVE_CLOCK_CONTROL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_CONTROL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_CONTROL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DS_TOPA_INST_OBSERVE_CLOCK_CONTROL :: DSA_OBSERVE_CLOCK_CONTROL [03:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_CONTROL_DSA_OBSERVE_CLOCK_CONTROL_MASK 0x0000000f |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_CONTROL_DSA_OBSERVE_CLOCK_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_CONTROL_DSA_OBSERVE_CLOCK_CONTROL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DS_TOPA_INST_OBSERVE_CLOCK_ENABLE - Ds topa inst observe clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_INST_OBSERVE_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_TOPA_INST_OBSERVE_CLOCK_ENABLE :: DSA_OBSERVE_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DSA_OBSERVE_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DSA_OBSERVE_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DSA_OBSERVE_CLOCK_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV - Ds topa inst observe clock enable div |
| ***************************************************************************/ |
| /* CLKGEN :: DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV :: DSA_OBSERVE_CLOCK_ENABLE_DIV [00:00] */ |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV_DSA_OBSERVE_CLOCK_ENABLE_DIV_MASK 0x00000001 |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV_DSA_OBSERVE_CLOCK_ENABLE_DIV_SHIFT 0 |
| #define BCHP_CLKGEN_DS_TOPA_INST_OBSERVE_CLOCK_ENABLE_DIV_DSA_OBSERVE_CLOCK_ENABLE_DIV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DTP_DFAP_TOP_INST_CLOCK_DISABLE - Disable DTP_DFAP_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_DTP_277_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_DTP_277_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_DTP_277_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_DTP_277_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_324_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_216_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_DTP_277_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_DTP_277_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_DTP_277_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_324_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_216_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DTP_DFAP_TOP_INST_CLOCK_ENABLE - Dtp dfap top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *EAGLET_TOP_INST_CLOCK_DISABLE - Disable EAGLET_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EAGLET_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_CORE_SLOWMIPS_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *EAGLET_TOP_INST_CLOCK_ENABLE - Eaglet top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: A15C_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: A15C_GISB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: A15C_CPU_C_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *EAGLET_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: A15C_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: A15C_GISB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: A15C_CPU_C_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *EAGLET_TOP_INST_ENABLE - Eaglet top inst enable |
| ***************************************************************************/ |
| /* CLKGEN :: EAGLET_TOP_INST_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: EAGLET_TOP_INST_ENABLE :: A15C_CPU_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_A15C_CPU_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_A15C_CPU_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_EAGLET_TOP_INST_ENABLE_A15C_CPU_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT - Egphy28 4port 33v 90o fc inst clock select |
| ***************************************************************************/ |
| /* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_REFCLK_CLOCK_SELECT [04:03] */ |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_REFCLK_CLOCK_SELECT_MASK 0x00000018 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_REFCLK_CLOCK_SELECT_SHIFT 3 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_REFCLK_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_BYPCLK_CLOCK_SELECT [02:02] */ |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_BYPCLK_CLOCK_SELECT_MASK 0x00000004 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_BYPCLK_CLOCK_SELECT_SHIFT 2 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_BYPCLK_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_25_54_CLOCK_SELECT [01:00] */ |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_54_CLOCK_SELECT_MASK 0x00000003 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_54_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_54_CLOCK_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE - Disable G2U_U2U_UBUS_MOD_SS_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE :: DISABLE_G2U_UBUS1_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_DISABLE_G2U_UBUS1_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_DISABLE_G2U_UBUS1_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_DISABLE_G2U_UBUS1_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS :: DISABLE_G2U_UBUS1_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS_DISABLE_G2U_UBUS1_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_DISABLE_STATUS_DISABLE_G2U_UBUS1_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE - G2u u2u ubus mod ss inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_GISB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_GISB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *INTERNAL_MUX_SELECT - Mux selects for Internal clocks |
| ***************************************************************************/ |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_TP_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_BPCM_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_DISABLE - Disable LEAP_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_27_UART_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_UART_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_ENABLE - Leap top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LEAP_TOP_INST_OBSERVE_CLOCK - Leap top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE - Disable MEMC0_DDR3_3390_TOP_WRAPPER_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE :: DISABLE_MEMC0_RBUS_108_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_MEMC0_RBUS_108_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_MEMC0_RBUS_108_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_MEMC0_RBUS_108_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: DISABLE_MEMC0_RBUS_108_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_MEMC0_RBUS_108_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_MEMC0_RBUS_108_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE - Memc0 ddr3 3390 top wrapper inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC0_SCB_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_SCB_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_SCB_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC0_MCLK_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_MCLK_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_MCLK_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_MCLK_CLOCK_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC0_GISB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_GISB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_GISB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC0_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC0_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC0_SCB_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC0_MCLK_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_MCLK_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_MCLK_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC0_GISB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_GISB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC0_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC0_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC0_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK - Memc0 ddr3 3390 top wrapper inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: MEMC0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: MEMC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: MEMC0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS - Memc0 ddr3 3390 top wrapper inst status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS :: MEMC0_PLL_LOCKED_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS_MEMC0_PLL_LOCKED_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC0_DDR3_3390_TOP_WRAPPER_INST_STATUS_MEMC0_PLL_LOCKED_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE - Disable MEMC1_DDR3_3390_TOP_WRAPPER_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE :: DISABLE_MEMC1_RBUS_108_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_MEMC1_RBUS_108_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_MEMC1_RBUS_108_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_MEMC1_RBUS_108_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: DISABLE_MEMC1_RBUS_108_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_MEMC1_RBUS_108_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_MEMC1_RBUS_108_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE - Memc1 ddr3 3390 top wrapper inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC1_SCB_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_SCB_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_SCB_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC1_MCLK_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_MCLK_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_MCLK_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_MCLK_CLOCK_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC1_GISB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_GISB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_GISB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC1_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE :: MEMC1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_MEMC1_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC1_SCB_CLOCK_ENABLE_STATUS [04:04] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC1_MCLK_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_MCLK_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_MCLK_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC1_GISB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_GISB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC1_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: MEMC1_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_MEMC1_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK - Memc1 ddr3 3390 top wrapper inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: MEMC1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: MEMC1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK :: MEMC1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_OBSERVE_CLOCK_MEMC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS - Memc1 ddr3 3390 top wrapper inst status |
| ***************************************************************************/ |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS :: MEMC1_PLL_LOCKED_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS_MEMC1_PLL_LOCKED_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMC1_DDR3_3390_TOP_WRAPPER_INST_STATUS_MEMC1_PLL_LOCKED_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCAMAC_TOP_INST_CLOCK_DISABLE - Disable MOCAMAC_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_TX_125_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_TX_125_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_TX_125_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_TX_125_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_25_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_200_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_TX_125_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_TX_125_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_TX_125_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_25_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_200_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTI_CLOCK_DISABLE - Disable MULTI's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_RDP_FPM_BROADBUS_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_FPM_BROADBUS_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_FPM_BROADBUS_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_FPM_BROADBUS_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_RDP_DOCSIS_BROADBUS_CLOCK [09:09] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_DOCSIS_BROADBUS_CLOCK_MASK 0x00000200 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_DOCSIS_BROADBUS_CLOCK_SHIFT 9 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_DOCSIS_BROADBUS_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_RDP_BYOI_BROADBUS_CLOCK [08:08] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_BYOI_BROADBUS_CLOCK_MASK 0x00000100 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_BYOI_BROADBUS_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_RDP_BYOI_BROADBUS_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_MCP_405_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_MCP_405_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_MCP_405_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_MCP_405_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_TP_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_SMISB_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_RBUS_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_RBUS_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_BPCM_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_RBUS_54_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_RBUS_54_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_RBUS_54_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_RBUS_54_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTI_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_RDP_FPM_BROADBUS_CLOCK_STATUS [10:10] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_RDP_FPM_BROADBUS_CLOCK_STATUS_MASK 0x00000400 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_RDP_FPM_BROADBUS_CLOCK_STATUS_SHIFT 10 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_RDP_DOCSIS_BROADBUS_CLOCK_STATUS [09:09] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_RDP_DOCSIS_BROADBUS_CLOCK_STATUS_MASK 0x00000200 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_RDP_DOCSIS_BROADBUS_CLOCK_STATUS_SHIFT 9 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_RDP_BYOI_BROADBUS_CLOCK_STATUS [08:08] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_RDP_BYOI_BROADBUS_CLOCK_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_RDP_BYOI_BROADBUS_CLOCK_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_MCP_405_CLOCK_STATUS [07:07] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_MCP_405_CLOCK_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_MCP_405_CLOCK_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS [06:06] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS [05:05] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_RBUS_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_RBUS_54_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_RBUS_54_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_RBUS_54_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_CLK_OUT0_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLK_OUT1_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE - Disable PAD's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_MUX_SELECT - Mux selects for Pad clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT1_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT0_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCIE_X2_TOP_INST_CLOCK_DISABLE - Disable PCIE_X2_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_RCBYPREF_100_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_RCBYPREF_100_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_RCBYPREF_100_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_RCBYPREF_100_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_RCBYPREF_100_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_RCBYPREF_100_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_RCBYPREF_100_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCIE_X2_TOP_INST_CLOCK_ENABLE - Pcie x2 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [03:03] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCIE_X2_TOP_INST_OBSERVE_CLOCK - Pcie x2 top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST - PLL_CPU_CORE Glitchless Clock Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f |
| |
| /* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS - PLL_CPU_CORE Glitchless Switching |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f |
| #define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CPU_CORE_PLL_RESET_STATUS - PLL_CPU_CORE Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_STRAP_OVERRIDE - Disable |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */ |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT_HIF [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_HIF_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_HIF_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_HIF_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [04:04] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK 0x00000010 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT 4 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_RDP [03:03] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_RDP_MASK 0x00000008 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_RDP_SHIFT 3 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_RDP_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU_CORE [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS1 [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS0 [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP - Power management LDO PLL |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC1 [04:04] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_SHIFT 4 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC0 [03:03] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_MASK 0x00000008 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_SHIFT 3 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_LC [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_DOCSIS_PLL_SYS2 [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RDP_TOP_WRAPPER_INST_CLOCK_DISABLE - Disable RDP_TOP_WRAPPER_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_DISABLE :: DISABLE_RDP_RUNNER_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_RDP_RUNNER_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_RDP_RUNNER_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_RDP_RUNNER_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_DISABLE :: DISABLE_RDP_NATCACHE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_RDP_NATCACHE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_RDP_NATCACHE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_DISABLE_RDP_NATCACHE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: DISABLE_RDP_RUNNER_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_RDP_RUNNER_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_RDP_RUNNER_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS :: DISABLE_RDP_NATCACHE_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_RDP_NATCACHE_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_DISABLE_STATUS_DISABLE_RDP_NATCACHE_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *RDP_TOP_WRAPPER_INST_CLOCK_ENABLE - Rdp top wrapper inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE :: RDP_MCP_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_MCP_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_MCP_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_MCP_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE :: RDP_GISB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_GISB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_GISB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE :: RDP_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_RDP_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: RDP_MCP_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_RDP_MCP_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_RDP_MCP_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: RDP_GISB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_RDP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_RDP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS :: RDP_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_RDP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_RDP_TOP_WRAPPER_INST_CLOCK_ENABLE_STATUS_RDP_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SECTOP_XPT_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_XPT_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_XPT_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_XPT_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SECTOP_XPT_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_XPT_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_XPT_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE - Spares |
| ***************************************************************************/ |
| /* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK 0xfffff000 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT 12 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */ |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK 0x00000fff |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT 0 |
| #define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SWITCH_TOP_INST_CLOCK_DISABLE - Disable SWITCH_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_SW_312P5_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_SW_312P5_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_SW_312P5_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_SW_312P5_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SWITCH_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SW_312P5_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SW_312P5_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SW_312P5_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SWITCH_TOP_INST_CLOCK_ENABLE - Switch top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SW_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SW_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SW_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SWITCH_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SW_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SW_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SW_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SWITCH_TOP_INST_OBSERVE_CLOCK - Switch top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SW_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SW_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SW_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SW_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *TCOFDM_TOP_INST_CLOCK_ENABLE - Tcofdm top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: TCOFDM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TCOFDM_TOP_INST_CLOCK_ENABLE :: TCO_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_TCO_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_TCO_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_TCO_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS :: TCO_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS_TCO_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_TCOFDM_TOP_INST_CLOCK_ENABLE_STATUS_TCO_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE - Disable TCQAM_DAVIC_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_TCQ_NCO_216_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_TCQ_NCO_216_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_TCQ_NCO_216_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_TCQ_NCO_216_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_TCQ_NCO_216_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_TCQ_NCO_216_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_TCQ_NCO_216_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE - Tcqam davic top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE :: TCQ_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_TCQ_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_TCQ_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_TCQ_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: TCQ_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_TCQ_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_TCQAM_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_TCQ_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *TESTPORT - Special Testport Controls |
| ***************************************************************************/ |
| /* CLKGEN :: TESTPORT :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */ |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x0000000f |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE - Disable UBUS_MOD_PERIPH_FPM_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_27_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_UBUS0_CLOCK [09:09] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_UBUS0_CLOCK_MASK 0x00000200 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_UBUS0_CLOCK_SHIFT 9 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_UBUS0_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_SPIM_100_CLOCK [08:08] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_MASK 0x00000100 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_RBUS_108_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_RBUS_108_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_RBUS_108_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_RBUS_108_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_OSC_54_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_OSC_54_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_OSC_54_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_OSC_54_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_HSPI_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_DEV_216_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_25_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_25_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_25_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_25_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_216_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_216_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_216_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_216_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_FPM_DEV_216_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_27_CLOCK_STATUS [10:10] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_MASK 0x00000400 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_SHIFT 10 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_UBUS0_CLOCK_STATUS [09:09] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_UBUS0_CLOCK_STATUS_MASK 0x00000200 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_UBUS0_CLOCK_STATUS_SHIFT 9 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_SPIM_100_CLOCK_STATUS [08:08] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_MASK 0x00000100 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_SHIFT 8 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_RBUS_108_CLOCK_STATUS [07:07] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_RBUS_108_CLOCK_STATUS_MASK 0x00000080 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_RBUS_108_CLOCK_STATUS_SHIFT 7 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_OSC_54_CLOCK_STATUS [06:06] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_OSC_54_CLOCK_STATUS_MASK 0x00000040 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_OSC_54_CLOCK_STATUS_SHIFT 6 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_HSPI_CLOCK_STATUS [05:05] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_MASK 0x00000020 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_SHIFT 5 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_DEV_216_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_25_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_25_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_25_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_216_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_216_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_216_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_FPM_DEV_216_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE - Ubus mod periph fpm inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE - Unimac mbdma top wan inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_DISABLE - Disable USB0_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_27_MDIO_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_27_MDIO_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_27_MDIO_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_27_MDIO_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_27_MDIO_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_27_MDIO_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_27_MDIO_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *USMAC_TOP_INST_CLOCK_ENABLE - Usmac top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USMAC_TOP_INST_CLOCK_ENABLE :: USMAC_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *USMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: USMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USMAC_TOP_INST_CLOCK_ENABLE_STATUS :: USMAC_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_USMAC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *US_TOP_INST_CLOCK_ENABLE - Us top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: US_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *US_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: US_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE - Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_USM_54_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_278_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_25_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_216_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_216_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_216_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_216_CLOCK_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_USM_54_CLOCK_STATUS [04:04] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_MASK 0x00000010 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_SHIFT 4 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_278_CLOCK_STATUS [03:03] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_MASK 0x00000008 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_SHIFT 3 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_25_CLOCK_STATUS [02:02] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_216_CLOCK_STATUS [01:01] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_216_CLOCK_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_216_CLOCK_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE - Utp crypto segdma top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: UTP_54_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: UTP_54_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *WOD_RCVR_TOPA_INST_CLOCK_ENABLE - Wod rcvr topa inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE :: WOD_A_GISB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_GISB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_GISB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_GISB_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE :: WOD_A_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE :: WOD_A_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_WOD_A_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS :: WOD_A_GISB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_WOD_A_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_WOD_A_GISB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS :: WOD_A_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_WOD_A_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_WOD_A_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS :: WOD_A_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_WOD_A_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPA_INST_CLOCK_ENABLE_STATUS_WOD_A_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *WOD_RCVR_TOPB_INST_CLOCK_ENABLE - Wod rcvr topb inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE :: WOD_B_GISB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_GISB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_GISB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_GISB_CLOCK_ENABLE_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE :: WOD_B_54_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_54_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_54_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_54_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE :: WOD_B_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_WOD_B_108_CLOCK_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status |
| ***************************************************************************/ |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS :: WOD_B_GISB_CLOCK_ENABLE_STATUS [02:02] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_WOD_B_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_WOD_B_GISB_CLOCK_ENABLE_STATUS_SHIFT 2 |
| |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS :: WOD_B_54_CLOCK_ENABLE_STATUS [01:01] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_WOD_B_54_CLOCK_ENABLE_STATUS_MASK 0x00000002 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_WOD_B_54_CLOCK_ENABLE_STATUS_SHIFT 1 |
| |
| /* CLKGEN :: WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS :: WOD_B_108_CLOCK_ENABLE_STATUS [00:00] */ |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_WOD_B_108_CLOCK_ENABLE_STATUS_MASK 0x00000001 |
| #define BCHP_CLKGEN_WOD_RCVR_TOPB_INST_CLOCK_ENABLE_STATUS_WOD_B_108_CLOCK_ENABLE_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *BSPI_CLOCK_SELECT - PLL RDB Macro Disable |
| ***************************************************************************/ |
| /* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */ |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0 |
| #define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MOCA_PLL_CTRL_WRAPPER_CONTROL - MOCA_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */ |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1 |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: MOCA_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LC_PLL_CTRL_WRAPPER_CONTROL - LC_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */ |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002 |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1 |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: LC_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_LC_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SC0_PLL_CTRL_WRAPPER_CONTROL - SC0_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */ |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002 |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1 |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SC0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_SC0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SC1_PLL_CTRL_WRAPPER_CONTROL - SC1_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: PWRDN_PLL_REQ [01:01] */ |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_MASK 0x00000002 |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_SHIFT 1 |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_PWRDN_PLL_REQ_DEFAULT 0x00000000 |
| |
| /* CLKGEN :: SC1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_SC1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *XPT_PLL_CTRL_WRAPPER_CONTROL - XPT_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: XPT_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: XPT_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_XPT_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RDP_PLL_CTRL_WRAPPER_CONTROL - RDP_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: RDP_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RDP_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RDP_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RDP_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_RDP_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RDP_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_RDP_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_PLL_CTRL_WRAPPER_CONTROL - CPU_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: CPU_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CPU_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_CPU_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL - DOCSISSYS0_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSISSYS0_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL - DOCSISSYS1_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSISSYS1_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL - DOCSISSYS2_PLL_CTRL_WRAPPER control |
| ***************************************************************************/ |
| /* CLKGEN :: DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL :: SW_SM_OVERRIDE [00:00] */ |
| #define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_SHIFT 0 |
| #define BCHP_CLKGEN_DOCSISSYS2_PLL_CTRL_WRAPPER_CONTROL_SW_SM_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CORE_XPT_HIF_BYP_CLOCK_SELECT - CORE_XPT_HIF_BYP_CLOCK_SELECT control |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_HIF_BYP_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_HIF_BYP_CLOCK_SELECT :: BYP_CLOCK_PIN_SEL [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_BYP_CLOCK_PIN_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_BYP_CLOCK_PIN_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_HIF_BYP_CLOCK_SELECT_BYP_CLOCK_PIN_SEL_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_CLKGEN_H__ */ |
| |
| /* End of File */ |
