| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Sat Jun 21 03:10:23 2014 |
| * Full Compile MD5 Checksum 2d7cd2763f1ef55897eaef5ea8fc6daa |
| * (minus title and desc) |
| * MD5 Checksum ad87f49099acb161d3ffa5d223fcb978 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_AON_PM_L2_H__ |
| #define BCHP_AON_PM_L2_H__ |
| |
| /*************************************************************************** |
| *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers |
| ***************************************************************************/ |
| #define BCHP_AON_PM_L2_CPU_STATUS 0x20410640 /* CPU interrupt Status Register */ |
| #define BCHP_AON_PM_L2_CPU_SET 0x20410644 /* CPU interrupt Set Register */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR 0x20410648 /* CPU interrupt Clear Register */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS 0x2041064c /* CPU interrupt Mask Status Register */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET 0x20410650 /* CPU interrupt Mask Set Register */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR 0x20410654 /* CPU interrupt Mask Clear Register */ |
| #define BCHP_AON_PM_L2_PCI_STATUS 0x20410658 /* PCI interrupt Status Register */ |
| #define BCHP_AON_PM_L2_PCI_SET 0x2041065c /* PCI interrupt Set Register */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR 0x20410660 /* PCI interrupt Clear Register */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS 0x20410664 /* PCI interrupt Mask Status Register */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET 0x20410668 /* PCI interrupt Mask Set Register */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR 0x2041066c /* PCI interrupt Mask Clear Register */ |
| |
| /*************************************************************************** |
| *CPU_STATUS - CPU interrupt Status Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_CPU_STATUS_DCS_PH3_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_CPU_STATUS_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_CPU_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_CPU_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_CPU_STATUS_DEMOD_XPT_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_CPU_STATUS_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_CPU_STATUS_AVS_WATCHDOG_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_CPU_STATUS_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_CPU_STATUS_RF4CE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_SET - CPU interrupt Set Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: CPU_SET :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_CPU_SET_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_CPU_SET_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_CPU_SET_DCS_PH3_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_CPU_SET_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_CPU_SET_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_CPU_SET_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_CPU_SET_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_CPU_SET_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_CPU_SET_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_CPU_SET_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_CPU_SET_DCS_HEADEND_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_CPU_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_CPU_SET_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_CPU_SET_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_CPU_SET_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_CPU_SET_DEMOD_XPT_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_CPU_SET_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_CPU_SET_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_CPU_SET_AVS_WATCHDOG_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_CPU_SET_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_CPU_SET_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_CPU_SET_RF4CE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_CLEAR - CPU interrupt Clear Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_DEMOD_XPT_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_RF4CE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU_MASK_STATUS - CPU interrupt Mask Status Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_PH3_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_DEMOD_XPT_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_AVS_WATCHDOG_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_RF4CE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CPU_MASK_SET - CPU interrupt Mask Set Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_PH3_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DCS_HEADEND_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_DEMOD_XPT_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_AVS_WATCHDOG_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_RF4CE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_DEMOD_XPT_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_RF4CE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PCI_STATUS - PCI interrupt Status Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_PCI_STATUS_DCS_PH3_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_PCI_STATUS_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_PCI_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_PCI_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_PCI_STATUS_DEMOD_XPT_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_PCI_STATUS_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_PCI_STATUS_AVS_WATCHDOG_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_PCI_STATUS_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_PCI_STATUS_RF4CE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCI_SET - PCI interrupt Set Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: PCI_SET :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_PCI_SET_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_PCI_SET_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_PCI_SET_DCS_PH3_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_PCI_SET_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_PCI_SET_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_PCI_SET_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_PCI_SET_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_PCI_SET_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_PCI_SET_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_PCI_SET_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_PCI_SET_DCS_HEADEND_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_PCI_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_PCI_SET_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_PCI_SET_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_PCI_SET_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_PCI_SET_DEMOD_XPT_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_PCI_SET_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_PCI_SET_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_PCI_SET_AVS_WATCHDOG_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_PCI_SET_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_PCI_SET_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_PCI_SET_RF4CE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCI_CLEAR - PCI interrupt Clear Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_STB_POWER_CYCLE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_DEMOD_XPT_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_RF4CE_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000000 |
| |
| /* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCI_MASK_STATUS - PCI interrupt Mask Status Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_PH3_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DCS_HEADEND_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_BATT_LOW_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_BMU_INTR_AP_LOST_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_DEMOD_XPT_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_AVS_WATCHDOG_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_RF4CE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PCI_MASK_SET - PCI interrupt Mask Set Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_PH3_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DCS_HEADEND_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_BATT_LOW_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_BMU_INTR_AP_LOST_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_DEMOD_XPT_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_AVS_WATCHDOG_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_RF4CE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:26] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xfc000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 26 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [25:25] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x02000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 25 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: DCS_PH3_RESET [24:24] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_PH3_RESET_MASK 0x01000000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_PH3_RESET_SHIFT 24 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_PH3_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SOFT_STB_POWER_CYCLE [23:23] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SOFT_STB_POWER_CYCLE_MASK 0x00800000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SOFT_STB_POWER_CYCLE_SHIFT 23 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SOFT_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: STB_POWER_CYCLE [22:22] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_STB_POWER_CYCLE_MASK 0x00400000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_STB_POWER_CYCLE_SHIFT 22 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_STB_POWER_CYCLE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [21:21] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK 0x00200000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT 21 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [20:20] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK 0x00100000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT 20 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: DCS_HEADEND_INTR [19:19] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_HEADEND_INTR_MASK 0x00080000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_HEADEND_INTR_SHIFT 19 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DCS_HEADEND_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: BMU_INTR_BATT_LOW [18:18] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_BATT_LOW_MASK 0x00040000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_BATT_LOW_SHIFT 18 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_BATT_LOW_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: BMU_INTR_AP_RESTORED [17:17] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_RESTORED_MASK 0x00020000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_RESTORED_SHIFT 17 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_RESTORED_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: BMU_INTR_AP_LOST [16:16] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_LOST_MASK 0x00010000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_LOST_SHIFT 16 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BMU_INTR_AP_LOST_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [15:15] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK 0x00008000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT 15 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [14:14] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK 0x00004000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT 14 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: DEMOD_XPT [13:13] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DEMOD_XPT_MASK 0x00002000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DEMOD_XPT_SHIFT 13 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_DEMOD_XPT_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK 0x00001000 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT 12 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_6 [11:11] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_6_MASK 0x00000800 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_6_SHIFT 11 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_6_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_5 [10:10] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_5_MASK 0x00000400 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_5_SHIFT 10 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_5_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_4 [09:09] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_4_MASK 0x00000200 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_4_SHIFT 9 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_4_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_3 [08:08] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_3_MASK 0x00000100 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_3_SHIFT 8 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_3_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: AVS_WATCHDOG [07:07] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_AVS_WATCHDOG_MASK 0x00000080 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_AVS_WATCHDOG_SHIFT 7 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_AVS_WATCHDOG_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: RF4CE [06:06] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_RF4CE_MASK 0x00000040 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_RF4CE_SHIFT 6 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_RF4CE_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK 0x00000020 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT 5 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK 0x00000010 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT 4 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK 0x00000008 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT 3 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK 0x00000004 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT 2 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_2 [01:01] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_2_MASK 0x00000002 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_2_SHIFT 1 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_2_DEFAULT 0x00000001 |
| |
| /* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_1 [00:00] */ |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_1_MASK 0x00000001 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_1_SHIFT 0 |
| #define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_1_DEFAULT 0x00000001 |
| |
| #endif /* #ifndef BCHP_AON_PM_L2_H__ */ |
| |
| /* End of File */ |
