| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Sat Apr 12 03:17:57 2014 |
| * Full Compile MD5 Checksum 5f2af4819d5a3039f3fe1938baf5d1f2 |
| * (minus title and desc) |
| * MD5 Checksum afc8344db5db4960ac3645d27d001fbc |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_XPT_MEMDMA_MCPB_CH0_H__ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_H__ |
| |
| /*************************************************************************** |
| *XPT_MEMDMA_MCPB_CH0 - MCPB Channel 0 Configuration |
| ***************************************************************************/ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL 0x00a60c00 /* MCPB Channel x Descriptor control information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL 0x00a60c04 /* MCPB Channel x Data control information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS 0x00a60c08 /* MCPB Channel x Current Descriptor address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS 0x00a60c0c /* MCPB Channel x Next Descriptor address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER 0x00a60c10 /* MCPB Channel x Data Buffer Base address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER 0x00a60c14 /* MCPB Channel x Data Buffer Base address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER 0x00a60c18 /* MCPB Channel x Data Buffer End address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER 0x00a60c1c /* MCPB Channel x Data Buffer End address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER 0x00a60c20 /* MCPB Channel x Current Data Buffer Read address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER 0x00a60c24 /* MCPB Channel x Current Data Buffer Read address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER 0x00a60c28 /* MCPB Channel x Data Buffer Write address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER 0x00a60c2c /* MCPB Channel x Data Buffer Write address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0 0x00a60c30 /* MCPB Channel x Status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1 0x00a60c34 /* MCPB Channel x CRC value */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2 0x00a60c38 /* MCPB Channel x Manual mode status */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0 0x00a60c3c /* MCPB channel x Descriptor Slot 0 status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1 0x00a60c40 /* MCPB channel x Descriptor Slot 0 status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR 0x00a60c44 /* MCPB Channel x Descriptor Slot 0 Current Descriptor Address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER 0x00a60c48 /* MCPB Channel x Descriptor Slot 0 Current Data Address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER 0x00a60c4c /* MCPB Channel x Descriptor Slot 0 Current Data Address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP 0x00a60c50 /* MCPB Channel x Descriptor Slot 0 Next Packet Timestamp */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA 0x00a60c54 /* MCPB Channel x Descriptor Slot 0 Packet to packet Timestamp delta */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0 0x00a60c58 /* MCPB channel x Descriptor Slot 1 status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1 0x00a60c5c /* MCPB channel x Descriptor Slot 1 status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR 0x00a60c60 /* MCPB Channel x Descriptor Slot 1 Current Descriptor Address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER 0x00a60c64 /* MCPB Channel x Descriptor Slot 1 Current Data Address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER 0x00a60c68 /* MCPB Channel x Descriptor Slot 1 Current Data Address */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP 0x00a60c6c /* MCPB Channel x Descriptor Slot 1 Next Packet Timestamp */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA 0x00a60c70 /* MCPB Channel x Descriptor Slot 1 Packet to packet Timestamp delta */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN 0x00a60c74 /* MCPB Channel x Packet length control */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL 0x00a60c78 /* MCPB Channel x Parser control */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1 0x00a60c7c /* MCPB Channel x Parser control 1 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG 0x00a60c80 /* MCPB Channel x TS Configuration */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG 0x00a60c84 /* MCPB Channel x PES and ES Configuration */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER 0x00a60c88 /* MCPB Channel x PES Sync counter */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG 0x00a60c8c /* MCPB Channel x ASF Configuration */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0 0x00a60c90 /* MCPB Channel x Stream Processor State Register 0 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1 0x00a60c94 /* MCPB Channel x Stream Processor State Register 1 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2 0x00a60c98 /* MCPB Channel x Stream Processor State Register 2 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3 0x00a60c9c /* MCPB Channel x Stream Processor State Register 3 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4 0x00a60ca0 /* MCPB Channel x Stream Processor State Register 4 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5 0x00a60ca4 /* MCPB Channel x Stream Processor State Register 5 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6 0x00a60ca8 /* MCPB Channel x Stream Processor State Register 6 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7 0x00a60cac /* MCPB Channel x Stream Processor State Register 7 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8 0x00a60cb0 /* MCPB Channel x Stream Processor State Register 8 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9 0x00a60cb4 /* MCPB Channel x Stream Processor State Register 9 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10 0x00a60cb8 /* MCPB Channel x Stream Processor State Register 10 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11 0x00a60cbc /* MCPB Channel x Stream Processor State Register 11 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12 0x00a60cc0 /* MCPB Channel x Stream Processor State Register 12 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13 0x00a60cc4 /* MCPB Channel x Stream Processor State Register 13 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL 0x00a60cc8 /* MCPB Channel x Burst buffer control */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC 0x00a60ccc /* MCPB Channel x Current CRC value */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS 0x00a60cd0 /* MCPB Channel x Burst buffer 0 data specific information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS 0x00a60cd4 /* MCPB Channel x Burst buffer 0 control specific information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS 0x00a60cd8 /* MCPB Channel x Burst buffer 1 data specific information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS 0x00a60cdc /* MCPB Channel x Burst buffer 1 control specific information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL 0x00a60ce0 /* MCPB Channel x Blockout control information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON 0x00a60ce4 /* MCPB Channel x next Blockout monitor information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL 0x00a60ce8 /* MCPB Channel x next Blockout monitor information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX 0x00a60cec /* MCPB Channel x reference difference value and next Timestamp information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY 0x00a60cf0 /* MCPB Channel x TS error bound early information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE 0x00a60cf4 /* MCPB Channel x TS error bound late information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON 0x00a60cf8 /* MCPB Channel x next Global Pacing Counter and Timestamp monitor information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN 0x00a60cfc /* MCPB Channel x reference difference value sign information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL 0x00a60d00 /* MCPB Channel x PES pacing control information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS 0x00a60d04 /* MCPB Channel x Slot 0 and Slot 1 information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1 0x00a60d08 /* MCPB Channel x timing information for Slot 0 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2 0x00a60d0c /* MCPB Channel x timing information for Slot 0 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1 0x00a60d10 /* MCPB Channel x timing information for Slot 1 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2 0x00a60d14 /* MCPB Channel x timing information for Slot 1 */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA 0x00a60d18 /* MCPB Channel x last TS delta value */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP 0x00a60d1c /* MCPB Channel x last NEXT TS value */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS 0x00a60d20 /* MCPB Channel x DCPM status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR 0x00a60d24 /* MCPB Channel x DCPM descriptor address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR 0x00a60d28 /* MCPB Channel x DCPM descriptor done interrupt address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL 0x00a60d2c /* MCPB Channel x Pause after group of packets control information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER 0x00a60d30 /* MCPB Channel x Pause after group of packets local packet counter */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER 0x00a60d34 /* MCPB Channel x local packet counter */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER 0x00a60d38 /* MCPB Channel x DCPM data address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER 0x00a60d3c /* MCPB Channel x DCPM data address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR 0x00a60d40 /* MCPB Channel x DCPM current descriptor address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS 0x00a60d44 /* MCPB Channel x DCPM slot status information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0 0x00a60d48 /* MCPB Channel x DCPM completed slot 0 descriptor address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER 0x00a60d4c /* MCPB Channel x DCPM completed slot 0 data address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER 0x00a60d50 /* MCPB Channel x DCPM completed slot 0 data address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1 0x00a60d54 /* MCPB Channel x DCPM completed slot 1 descriptor address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER 0x00a60d58 /* MCPB Channel x DCPM completed slot 1 data address information */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER 0x00a60d5c /* MCPB Channel x DCPM completed slot 1 data address information */ |
| |
| /*************************************************************************** |
| *DMA_DESC_CONTROL - MCPB Channel x Descriptor control information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: FIRST_DESC_ADDRESS [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_FIRST_DESC_ADDRESS_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_FIRST_DESC_ADDRESS_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: reserved0 [03:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_reserved0_MASK 0x0000000c |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_reserved0_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: LLD_TYPE [01:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_LLD_TYPE_MASK 0x00000003 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_LLD_TYPE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DATA_CONTROL - MCPB Channel x Data control information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: reserved0 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_reserved0_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_reserved0_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: RUN_VERSION [15:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_RUN_VERSION_MASK 0x0000f800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_RUN_VERSION_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: ENDIAN_CONTROL [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_ENDIAN_CONTROL_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_ENDIAN_CONTROL_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: DRAM_REQ_SIZE [09:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_DRAM_REQ_SIZE_MASK 0x000003ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_DRAM_REQ_SIZE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_CURR_DESC_ADDRESS - MCPB Channel x Current Descriptor address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_CURR_DESC_ADDRESS :: CURR_DESC_ADDRESS [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_CURR_DESC_ADDRESS_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_CURR_DESC_ADDRESS_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_CURR_DESC_ADDRESS :: reserved0 [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_reserved0_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_NEXT_DESC_ADDRESS - MCPB Channel x Next Descriptor address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_NEXT_DESC_ADDRESS :: NEXT_DESC_ADDRESS [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_NEXT_DESC_ADDRESS_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_NEXT_DESC_ADDRESS_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_NEXT_DESC_ADDRESS :: reserved0 [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_reserved0_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_BASE_ADDRESS_UPPER - MCPB Channel x Data Buffer Base address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_UPPER :: BUFF_BASE_ADDRESS [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_BUFF_BASE_ADDRESS_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_BUFF_BASE_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_BASE_ADDRESS_LOWER - MCPB Channel x Data Buffer Base address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_LOWER :: BUFF_BASE_ADDRESS [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER_BUFF_BASE_ADDRESS_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER_BUFF_BASE_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_END_ADDRESS_UPPER - MCPB Channel x Data Buffer End address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_UPPER :: BUFF_END_ADDRESS [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_BUFF_END_ADDRESS_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_BUFF_END_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_END_ADDRESS_LOWER - MCPB Channel x Data Buffer End address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_LOWER :: BUFF_END_ADDRESS [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER_BUFF_END_ADDRESS_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER_BUFF_END_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_CURR_RD_ADDRESS_UPPER - MCPB Channel x Current Data Buffer Read address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_UPPER :: BUFF_CURR_RD_ADDRESS [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_BUFF_CURR_RD_ADDRESS_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_BUFF_CURR_RD_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_CURR_RD_ADDRESS_LOWER - MCPB Channel x Current Data Buffer Read address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_LOWER :: BUFF_CURR_RD_ADDRESS [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER_BUFF_CURR_RD_ADDRESS_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER_BUFF_CURR_RD_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_WRITE_ADDRESS_UPPER - MCPB Channel x Data Buffer Write address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_UPPER :: BUFF_WRITE_ADDRESS [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_BUFF_WRITE_ADDRESS_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_BUFF_WRITE_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BUFF_WRITE_ADDRESS_LOWER - MCPB Channel x Data Buffer Write address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_LOWER :: BUFF_WRITE_ADDRESS [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER_BUFF_WRITE_ADDRESS_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER_BUFF_WRITE_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_STATUS_0 - MCPB Channel x Status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: reserved0 [31:31] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_reserved0_MASK 0x80000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_reserved0_SHIFT 31 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_SLOT_NUM_TO_USE [30:30] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_SLOT_NUM_TO_USE_MASK 0x40000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_SLOT_NUM_TO_USE_SHIFT 30 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_0B_BAND_ID_CHANGE_TRANS [29:29] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_BAND_ID_CHANGE_TRANS_MASK 0x20000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_BAND_ID_CHANGE_TRANS_SHIFT 29 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_0B_CONTROL_TRANS [28:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_CONTROL_TRANS_MASK 0x10000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_CONTROL_TRANS_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_RESET_PARSER_ON_1ST_NON_0_TRAN [27:27] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_RESET_PARSER_ON_1ST_NON_0_TRAN_MASK 0x08000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_RESET_PARSER_ON_1ST_NON_0_TRAN_SHIFT 27 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: FIRST_DESC_RD_AFTER_RUN_ASSERT [26:26] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FIRST_DESC_RD_AFTER_RUN_ASSERT_MASK 0x04000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FIRST_DESC_RD_AFTER_RUN_ASSERT_SHIFT 26 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: ZERO_BYTE_DESC [25:25] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_ZERO_BYTE_DESC_MASK 0x02000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_ZERO_BYTE_DESC_SHIFT 25 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: LAST_DESC_IND [24:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_LAST_DESC_IND_MASK 0x01000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_LAST_DESC_IND_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: HOST_DATA_INS_EN [23:23] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_HOST_DATA_INS_EN_MASK 0x00800000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_HOST_DATA_INS_EN_SHIFT 23 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: FORCE_RESYNC [22:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FORCE_RESYNC_MASK 0x00400000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FORCE_RESYNC_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PUSH_PREV_PARTIAL_PACKET [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PREV_PARTIAL_PACKET_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PREV_PARTIAL_PACKET_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PUSH_PARTIAL_PACKET [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PARTIAL_PACKET_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PARTIAL_PACKET_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_BAND_ID [19:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_MASK 0x000ff000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_BAND_ID_EN [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_EN_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_EN_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_PARSER_SEL [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_PARSER_SEL_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_PARSER_SEL_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: RD_ENDIAN_STRAP_INV_CTRL [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_RD_ENDIAN_STRAP_INV_CTRL_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_RD_ENDIAN_STRAP_INV_CTRL_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_LOAD [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_LOAD_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_LOAD_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_COMPARE [07:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPARE_MASK 0x00000080 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPARE_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_COMPUTE [06:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPUTE_MASK 0x00000040 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPUTE_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SCRAM_START [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_START_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_START_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SCRAM_END [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_END_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_END_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: NEXT_TIMESTAMP_VALID [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PAUSE_AT_DESC_READ [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_READ_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_READ_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PAUSE_AT_DESC_END [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_END_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_END_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_STATUS_1 - MCPB Channel x CRC value |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_1 :: CRC_IN [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1_CRC_IN_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1_CRC_IN_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_STATUS_2 - MCPB Channel x Manual mode status |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: reserved0 [31:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_reserved0_MASK 0xfffffff8 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_reserved0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: SP_COMMAND_FROM_DESC_TYPE [02:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_TYPE_MASK 0x00000006 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_TYPE_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: SP_COMMAND_FROM_DESC_EN [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_EN_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_EN_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_STATUS_0 - MCPB channel x Descriptor Slot 0 status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: reserved0 [31:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_reserved0_MASK 0xfff80000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_reserved0_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: INTR_EN [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_INTR_EN_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_INTR_EN_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PAUSE_AT_DESCRIPTOR_READ [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PAUSE_AT_DESCRIPTOR_END [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_END_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_END_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: DESC_ID [15:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_DESC_ID_MASK 0x0000f000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_DESC_ID_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: RANDOM_ACCESS_IND [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RANDOM_ACCESS_IND_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RANDOM_ACCESS_IND_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: RUN_VERSION [10:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RUN_VERSION_MASK 0x000007c0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RUN_VERSION_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: HOST_DATA_INS_AS_BTP_PKT [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_START [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_START_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_START_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_END [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_END_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_END_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_INIT [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_INIT_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_INIT_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: NEXT_TIMESTAMP_VALID [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_STATUS_1 - MCPB channel x Descriptor Slot 0 status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: reserved0 [31:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_reserved0_MASK 0xffe00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_reserved0_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_BAND_ID_EN [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_EN_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_EN_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_PARSER_SEL [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_PARSER_SEL_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_PARSER_SEL_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_BAND_ID [18:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_MASK 0x0007f800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: PID_CHANNEL_VALID [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_VALID_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_VALID_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: PID_CHANNEL [09:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_MASK 0x000003ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_CURR_DESC_ADDR - MCPB Channel x Descriptor Slot 0 Current Descriptor Address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER - MCPB Channel x Descriptor Slot 0 Current Data Address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER :: CUR_DATA_ADDR [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER - MCPB Channel x Descriptor Slot 0 Current Data Address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER :: CUR_DATA_ADDR [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_NEXT_TIMESTAMP - MCPB Channel x Descriptor Slot 0 Next Packet Timestamp |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_NEXT_TIMESTAMP :: NEXT_TIMESTAMP [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP_NEXT_TIMESTAMP_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP_NEXT_TIMESTAMP_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA - MCPB Channel x Descriptor Slot 0 Packet to packet Timestamp delta |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA :: PKT2PKT_TIMESTAMP_DELTA [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_STATUS_0 - MCPB channel x Descriptor Slot 1 status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: reserved0 [31:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_reserved0_MASK 0xfff80000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_reserved0_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: INTR_EN [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_INTR_EN_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_INTR_EN_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PAUSE_AT_DESCRIPTOR_READ [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PAUSE_AT_DESCRIPTOR_END [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_END_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_END_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: DESC_ID [15:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_DESC_ID_MASK 0x0000f000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_DESC_ID_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: RANDOM_ACCESS_IND [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RANDOM_ACCESS_IND_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RANDOM_ACCESS_IND_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: RUN_VERSION [10:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RUN_VERSION_MASK 0x000007c0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RUN_VERSION_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: HOST_DATA_INS_AS_BTP_PKT [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_START [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_START_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_START_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_END [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_END_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_END_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_INIT [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_INIT_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_INIT_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: NEXT_TIMESTAMP_VALID [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_STATUS_1 - MCPB channel x Descriptor Slot 1 status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: reserved0 [31:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_reserved0_MASK 0xffe00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_reserved0_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_BAND_ID_EN [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_EN_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_EN_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_PARSER_SEL [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_PARSER_SEL_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_PARSER_SEL_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_BAND_ID [18:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_MASK 0x0007f800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: PID_CHANNEL_VALID [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_VALID_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_VALID_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: PID_CHANNEL [09:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_MASK 0x000003ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_CURR_DESC_ADDR - MCPB Channel x Descriptor Slot 1 Current Descriptor Address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER - MCPB Channel x Descriptor Slot 1 Current Data Address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER :: CUR_DATA_ADDR [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER - MCPB Channel x Descriptor Slot 1 Current Data Address |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER :: CUR_DATA_ADDR [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_NEXT_TIMESTAMP - MCPB Channel x Descriptor Slot 1 Next Packet Timestamp |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_NEXT_TIMESTAMP :: NEXT_TIMESTAMP [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP_NEXT_TIMESTAMP_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP_NEXT_TIMESTAMP_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA - MCPB Channel x Descriptor Slot 1 Packet to packet Timestamp delta |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA :: PKT2PKT_TIMESTAMP_DELTA [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_PKT_LEN - MCPB Channel x Packet length control |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PKT_LEN :: PACKET_LENGTH [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN_PACKET_LENGTH_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN_PACKET_LENGTH_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_PARSER_CTRL - MCPB Channel x Parser control |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved0 [31:26] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved0_MASK 0xfc000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved0_SHIFT 26 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL [25:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL_MASK 0x03000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: STANDALONE_BLOCK_MODE_EN [23:23] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_EN_MASK 0x00800000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_EN_SHIFT 23 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: SCRAM_START_END_FOR_EVERY_PACKET [22:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_SCRAM_START_END_FOR_EVERY_PACKET_MASK 0x00400000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_SCRAM_START_END_FOR_EVERY_PACKET_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved1 [21:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved1_MASK 0x003c0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved1_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PUSI_SET_DIS [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PUSI_SET_DIS_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PUSI_SET_DIS_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved2 [16:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved2_MASK 0x00018000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved2_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PB_PARSER_SEL [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_SEL_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_SEL_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PB_PARSER_BAND_ID [13:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_BAND_ID_MASK 0x00003fc0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_BAND_ID_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved3 [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved3_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved3_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_ALL_PASS_CTRL [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ALL_PASS_CTRL_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ALL_PASS_CTRL_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_STREAM_TYPE [03:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_STREAM_TYPE_MASK 0x0000000e |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_STREAM_TYPE_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_ENABLE [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ENABLE_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ENABLE_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_PARSER_CTRL1 - MCPB Channel x Parser control 1 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: reserved0 [31:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_reserved0_MASK 0xffffe000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_reserved0_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: PIDP_DEBUG_MODE [12:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_PIDP_DEBUG_MODE_MASK 0x00001000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_PIDP_DEBUG_MODE_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: ALL_PASS_PID_CH_NUM [11:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_ALL_PASS_PID_CH_NUM_MASK 0x00000fff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_ALL_PASS_PID_CH_NUM_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_TS_CONFIG - MCPB Channel x TS Configuration |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved0 [31:31] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved0_MASK 0x80000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved0_SHIFT 31 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_AFID [30:30] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFID_MASK 0x40000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFID_SHIFT 30 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_CFF [29:29] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CFF_MASK 0x20000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CFF_SHIFT 29 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_RTS00 [28:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_RTS00_MASK 0x10000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_RTS00_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_AFS [27:27] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFS_MASK 0x08000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFS_SHIFT 27 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_CC [26:26] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CC_MASK 0x04000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CC_SHIFT 26 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_OCF [25:25] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_OCF_MASK 0x02000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_OCF_SHIFT 25 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_SCF [24:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_SCF_MASK 0x01000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_SCF_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved1 [23:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved1_MASK 0x00e00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved1_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: PCR_PACING_PID [20:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PCR_PACING_PID_MASK 0x001fff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PCR_PACING_PID_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved2 [07:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved2_MASK 0x000000c0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved2_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: INPUT_TEI_IGNORE [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_TEI_IGNORE_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_TEI_IGNORE_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved3 [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved3_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved3_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: PARSER_ACCEPT_NULL_PKT [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PARSER_ACCEPT_NULL_PKT_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PARSER_ACCEPT_NULL_PKT_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: ATS_PARITY_CHECK_DIS [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_ATS_PARITY_CHECK_DIS_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_ATS_PARITY_CHECK_DIS_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: INPUT_HAS_ATS [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_HAS_ATS_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_HAS_ATS_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: MPEG_TS_AUTO_SYNC_DETECT [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_MPEG_TS_AUTO_SYNC_DETECT_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_MPEG_TS_AUTO_SYNC_DETECT_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_PES_ES_CONFIG - MCPB Channel x PES and ES Configuration |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: reserved0 [31:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_reserved0_MASK 0xffc00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_reserved0_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PKTZ_SC [21:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PKTZ_SC_MASK 0x00300000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PKTZ_SC_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: STREAM_ID_EXT_EN [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_STREAM_ID_EXT_EN_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_STREAM_ID_EXT_EN_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SUB_STREAM_ID_EXT_EN [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SUB_STREAM_ID_EXT_EN_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SUB_STREAM_ID_EXT_EN_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PROGRAM_STREAM_EN [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_EN_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_EN_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PROGRAM_STREAM_MODE [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_MODE_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_MODE_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SYNC_ID_HIGH [15:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_HIGH_MASK 0x0000ff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_HIGH_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SYNC_ID_LOW [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_LOW_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_LOW_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_PES_SYNC_COUNTER - MCPB Channel x PES Sync counter |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_PES_SYNC_COUNTER :: PES_SYNC_COUNTER [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER_PES_SYNC_COUNTER_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER_PES_SYNC_COUNTER_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_ASF_CONFIG - MCPB Channel x ASF Configuration |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved0 [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved0_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved0_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_PAYLOAD_SPACE [23:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SPACE_MASK 0x00ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SPACE_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved1 [15:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved1_MASK 0x0000f000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved1_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_DATA_PACKET_LENGTH_VALID [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_DATA_PACKET_LENGTH_VALID_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_DATA_PACKET_LENGTH_VALID_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_ADAPTIVE_PACKET_LENGTH_ENABLE [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_ADAPTIVE_PACKET_LENGTH_ENABLE_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_ADAPTIVE_PACKET_LENGTH_ENABLE_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_PAYLOAD_SC [09:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SC_MASK 0x00000300 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SC_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_SUB_PAYLOAD_SC [07:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_SUB_PAYLOAD_SC_MASK 0x000000c0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_SUB_PAYLOAD_SC_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved2 [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved2_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved2_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TYPE_80_GEN_EN [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_80_GEN_EN_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_80_GEN_EN_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TYPE_8F_GEN_EN [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_8F_GEN_EN_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_8F_GEN_EN_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TEST_HALT [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TEST_HALT_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TEST_HALT_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_STREAM_LENGTH_ENDIANESS [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_STREAM_LENGTH_ENDIANESS_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_STREAM_LENGTH_ENDIANESS_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved3 [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved3_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved3_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_0 - MCPB Channel x Stream Processor State Register 0 |
| ***************************************************************************/ |
| /* union - case NON_BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE4 [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE4_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE4_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE3 [23:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE3_MASK 0x00ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE3_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE2 [15:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE2_MASK 0x0000ff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE2_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE1 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE1_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE1_SHIFT 0 |
| |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: BLOCK_MODE :: RA1_WORD5 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_BLOCK_MODE_RA1_WORD5_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_BLOCK_MODE_RA1_WORD5_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_1 - MCPB Channel x Stream Processor State Register 1 |
| ***************************************************************************/ |
| /* union - case MPEG [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DATA_ACCUM_VALID [31:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DATA_ACCUM_VALID_MASK 0xf0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DATA_ACCUM_VALID_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: TS_STATE [27:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TS_STATE_MASK 0x0fc00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TS_STATE_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: OUT_OF_SYNC [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_OUT_OF_SYNC_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_OUT_OF_SYNC_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: TIMESTAMP_VALID [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TIMESTAMP_VALID_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TIMESTAMP_VALID_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: ADP_CNTL_1 [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_CNTL_1_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_CNTL_1_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: ADP_LEN [18:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_LEN_MASK 0x0007f800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_LEN_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DISCONT_IND [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DISCONT_IND_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DISCONT_IND_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: PCR_FLAG [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_PCR_FLAG_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_PCR_FLAG_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved0 [08:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved0_MASK 0x00000180 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved0_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DESC_BASE_PACING [06:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DESC_BASE_PACING_MASK 0x00000040 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DESC_BASE_PACING_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved1 [05:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved1_MASK 0x00000038 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved1_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: SMU_PKT_DROP [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_SMU_PKT_DROP_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_SMU_PKT_DROP_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved2 [01:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved2_MASK 0x00000003 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved2_SHIFT 0 |
| |
| /* union - case DSS [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: DATA_ACCUM_VALID [31:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DATA_ACCUM_VALID_MASK 0xf0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DATA_ACCUM_VALID_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: TS_STATE [27:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TS_STATE_MASK 0x0fc00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TS_STATE_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: OUT_OF_SYNC [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_OUT_OF_SYNC_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_OUT_OF_SYNC_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: TIMESTAMP_VALID [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TIMESTAMP_VALID_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TIMESTAMP_VALID_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: CC_ZERO [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CC_ZERO_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CC_ZERO_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: HD_ZERO [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_HD_ZERO_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_HD_ZERO_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: CFF_ONE [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CFF_ONE_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CFF_ONE_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: AFID_THREE [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFID_THREE_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFID_THREE_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: AFS_7D [15:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFS_7D_MASK 0x00008000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFS_7D_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: RTS00 [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_RTS00_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_RTS00_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: ORIG_CF [13:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_ORIG_CF_MASK 0x00002000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_ORIG_CF_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: PF [12:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_PF_MASK 0x00001000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_PF_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved0 [11:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved0_MASK 0x00000f80 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved0_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: DESC_BASE_PACING [06:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DESC_BASE_PACING_MASK 0x00000040 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DESC_BASE_PACING_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved1 [05:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved1_MASK 0x00000038 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved1_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: SMU_PKT_DROP [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_SMU_PKT_DROP_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_SMU_PKT_DROP_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved2 [01:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved2_MASK 0x00000003 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved2_SHIFT 0 |
| |
| /* union - case PES_ES_RAW [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: DATA_ACCUM_VALID [31:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DATA_ACCUM_VALID_MASK 0xf0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DATA_ACCUM_VALID_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_STATE [27:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_STATE_MASK 0x0fc00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_STATE_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: OUT_OF_SYNC [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_OUT_OF_SYNC_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_OUT_OF_SYNC_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PTS_DTS_FLAGS [20:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PTS_DTS_FLAGS_MASK 0x00180000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PTS_DTS_FLAGS_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: ESCR_FLAG [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ESCR_FLAG_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ESCR_FLAG_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: ES_RATE_FLAG [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ES_RATE_FLAG_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ES_RATE_FLAG_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: DSM_TRICK_MODE_FLAG [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DSM_TRICK_MODE_FLAG_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DSM_TRICK_MODE_FLAG_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: COPY_INFO_FLAG [15:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_COPY_INFO_FLAG_MASK 0x00008000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_COPY_INFO_FLAG_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_CRC_FLAG [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_CRC_FLAG_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_CRC_FLAG_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_EXT1_FLAG [13:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT1_FLAG_MASK 0x00002000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT1_FLAG_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_PRIVATE_DATA_FLAG [12:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_PRIVATE_DATA_FLAG_MASK 0x00001000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_PRIVATE_DATA_FLAG_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PHF_FLAG [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PHF_FLAG_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PHF_FLAG_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PGRM_PKT_SEQ_FLAG [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PGRM_PKT_SEQ_FLAG_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PGRM_PKT_SEQ_FLAG_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PSTD_BUFFER_FLAG [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PSTD_BUFFER_FLAG_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PSTD_BUFFER_FLAG_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_EXT2_FLAG [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT2_FLAG_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT2_FLAG_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: reserved0 [07:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved0_MASK 0x000000f8 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: SMU_PKT_DROP [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_SMU_PKT_DROP_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_SMU_PKT_DROP_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: NEW_PKT_START [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_NEW_PKT_START_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_NEW_PKT_START_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: reserved1 [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved1_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved1_SHIFT 0 |
| |
| /* union - case ASF [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: DATA_ACCUM_VALID [31:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_DATA_ACCUM_VALID_MASK 0xf0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_DATA_ACCUM_VALID_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: ASF_STATE [27:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_ASF_STATE_MASK 0x0fe00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_ASF_STATE_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: SEQUENCE_TYPE [20:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SEQUENCE_TYPE_MASK 0x00180000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SEQUENCE_TYPE_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PADDING_LEN_TYPE [18:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PADDING_LEN_TYPE_MASK 0x00060000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PADDING_LEN_TYPE_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PKT_LEN_TYPE [16:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PKT_LEN_TYPE_MASK 0x00018000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PKT_LEN_TYPE_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: REP_DATA_LEN_TYPE [14:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_TYPE_MASK 0x00006000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_TYPE_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: OFS_2MED_OBJ_NUM_LEN_TYPE [12:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_NUM_LEN_TYPE_MASK 0x00001800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_NUM_LEN_TYPE_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: MD_OBJ_LEN_TYPE [10:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MD_OBJ_LEN_TYPE_MASK 0x00000600 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MD_OBJ_LEN_TYPE_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PAYLD_LEN_TYPE [08:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PAYLD_LEN_TYPE_MASK 0x00000180 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PAYLD_LEN_TYPE_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: MUL_PAYLD_PRESENT [06:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MUL_PAYLD_PRESENT_MASK 0x00000040 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MUL_PAYLD_PRESENT_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: REP_DATA_LEN_EQ_ONE [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_EQ_ONE_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_EQ_ONE_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: reserved0 [04:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved0_MASK 0x00000018 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: SMU_PKT_DROP [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SMU_PKT_DROP_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SMU_PKT_DROP_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: OFS_2MED_OBJ_LEN_ZERO [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_LEN_ZERO_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_LEN_ZERO_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: reserved1 [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved1_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved1_SHIFT 0 |
| |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: BLOCK_MODE :: RA1_WORD4 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_BLOCK_MODE_RA1_WORD4_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_BLOCK_MODE_RA1_WORD4_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_2 - MCPB Channel x Stream Processor State Register 2 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: reserved0 [31:30] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_reserved0_MASK 0xc0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_reserved0_SHIFT 30 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PT_SEARCH_DONE [29:29] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_SEARCH_DONE_MASK 0x20000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_SEARCH_DONE_SHIFT 29 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PT_MATCH [28:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_MATCH_MASK 0x10000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_MATCH_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PKT_CH_NUM [27:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_CH_NUM_MASK 0x0fff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_CH_NUM_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PKT_DESTINATION [15:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_DESTINATION_MASK 0x0000ffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_DESTINATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_3 - MCPB Channel x Stream Processor State Register 3 |
| ***************************************************************************/ |
| /* union - case MPEG [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PID [31:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PID_MASK 0xfff80000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PID_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PCR_FIRST_PKT_AFT_FUN_ASSERT [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FIRST_PKT_AFT_FUN_ASSERT_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FIRST_PKT_AFT_FUN_ASSERT_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: reserved0 [16:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved0_MASK 0x0001fc00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved0_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: FORCE_RESYNC [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FORCE_RESYNC_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FORCE_RESYNC_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PCR_FORCE_RESYNC [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FORCE_RESYNC_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FORCE_RESYNC_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: reserved1 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved1_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved1_SHIFT 0 |
| |
| /* union - case DSS [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: SCID [31:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_SCID_MASK 0xfff80000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_SCID_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: PCR_FIRST_PKT_AFT_FUN_ASSERT [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FIRST_PKT_AFT_FUN_ASSERT_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FIRST_PKT_AFT_FUN_ASSERT_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: reserved0 [16:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved0_MASK 0x0001fc00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved0_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: FORCE_RESYNC [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FORCE_RESYNC_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FORCE_RESYNC_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: PCR_FORCE_RESYNC [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FORCE_RESYNC_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FORCE_RESYNC_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: reserved1 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved1_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved1_SHIFT 0 |
| |
| /* union - case PES_or_ES_or_RAW [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: PID [31:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PID_MASK 0xfff80000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PID_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: PUSI [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PUSI_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PUSI_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: RAI [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: RAI_LEVEL_1 [15:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_LEVEL_1_MASK 0x00008000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_LEVEL_1_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved0 [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved0_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved0_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: AFC [13:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_AFC_MASK 0x00003000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_AFC_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved1 [11:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved1_MASK 0x00000c00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved1_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: FORCE_RESYNC [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FORCE_RESYNC_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FORCE_RESYNC_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved2 [08:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved2_MASK 0x000001ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved2_SHIFT 0 |
| |
| /* union - case ASF [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: PID [31:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PID_MASK 0xfff80000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PID_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: PUSI [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PUSI_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PUSI_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: RAI [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: RAI_LEVEL_1 [15:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_LEVEL_1_MASK 0x00008000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_LEVEL_1_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved0 [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved0_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved0_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: AFC [13:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_AFC_MASK 0x00003000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_AFC_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved1 [11:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved1_MASK 0x00000c00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved1_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: FORCE_RESYNC [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FORCE_RESYNC_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FORCE_RESYNC_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved2 [08:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved2_MASK 0x000001c0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved2_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: NUM_OF_PAYLD [05:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_NUM_OF_PAYLD_MASK 0x0000003f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_NUM_OF_PAYLD_SHIFT 0 |
| |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: BLOCK_MODE :: RA1_WORD3 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_BLOCK_MODE_RA1_WORD3_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_BLOCK_MODE_RA1_WORD3_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_4 - MCPB Channel x Stream Processor State Register 4 |
| ***************************************************************************/ |
| /* union - case MPEG_or_DSS [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: MPEG_or_DSS :: GEN_COUNT0 [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_GEN_COUNT0_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_GEN_COUNT0_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: MPEG_or_DSS :: reserved0 [23:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_reserved0_MASK 0x00ffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_reserved0_SHIFT 0 |
| |
| /* union - case PES_or_ES_or_RAW [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: GEN_COUNT0 [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_GEN_COUNT0_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_GEN_COUNT0_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: reserved0 [23:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved0_MASK 0x00ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved0_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: PAYLD_SECT_LEN [15:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_PAYLD_SECT_LEN_MASK 0x0000ff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_PAYLD_SECT_LEN_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: reserved1 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved1_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved1_SHIFT 0 |
| |
| /* union - case ASF [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: GEN_COUNT0 [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_GEN_COUNT0_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_GEN_COUNT0_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: PRIVATE_DATA_SECT_LEN [23:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PRIVATE_DATA_SECT_LEN_MASK 0x00ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PRIVATE_DATA_SECT_LEN_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: PAYLD_SECT_LEN [15:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PAYLD_SECT_LEN_MASK 0x0000ff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PAYLD_SECT_LEN_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: reserved0 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_reserved0_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_reserved0_SHIFT 0 |
| |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: BLOCK_MODE :: RA1_WORD2 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_BLOCK_MODE_RA1_WORD2_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_BLOCK_MODE_RA1_WORD2_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_5 - MCPB Channel x Stream Processor State Register 5 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_5 :: GEN_COUNT1 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5_GEN_COUNT1_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5_GEN_COUNT1_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_6 - MCPB Channel x Stream Processor State Register 6 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_6 :: GEN_COUNT2 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6_GEN_COUNT2_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6_GEN_COUNT2_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_7 - MCPB Channel x Stream Processor State Register 7 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_7 :: GEN_COUNT3 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7_GEN_COUNT3_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7_GEN_COUNT3_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_8 - MCPB Channel x Stream Processor State Register 8 |
| ***************************************************************************/ |
| /* union - case MPEG [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: MPEG :: PCR_BASE [31:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_BASE_MASK 0xfffffe00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_BASE_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: MPEG :: PCR_EXT [08:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_EXT_MASK 0x000001ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_EXT_SHIFT 0 |
| |
| /* union - case DSS [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: DSS :: RTS [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_DSS_RTS_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_DSS_RTS_SHIFT 0 |
| |
| /* union - case PES_or_ES_or_RAW [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_EXT [23:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_MASK 0x00ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: SUB_ID [15:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_MASK 0x0000ff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_VALID [07:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_VALID_MASK 0x00000080 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_VALID_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_EXT_VALID [06:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_VALID_MASK 0x00000040 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_VALID_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: SUB_ID_VALID [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_VALID_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_VALID_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: reserved0 [04:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_reserved0_MASK 0x0000001f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_reserved0_SHIFT 0 |
| |
| /* union - case ASF [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: ASF :: ASF_PKT_LEN [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_ASF_ASF_PKT_LEN_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_ASF_ASF_PKT_LEN_SHIFT 0 |
| |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: BLOCK_MODE :: RA1_WORD1 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_BLOCK_MODE_RA1_WORD1_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_BLOCK_MODE_RA1_WORD1_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_9 - MCPB Channel x Stream Processor State Register 9 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: DRAM_REGION [31:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_DRAM_REGION_MASK 0xff000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_DRAM_REGION_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SEC_OP_PIPE_SEL [23:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SEC_OP_PIPE_SEL_MASK 0x00c00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SEC_OP_PIPE_SEL_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SECONDARY_PACKET [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SECONDARY_PACKET_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SECONDARY_PACKET_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SPID_VERSION [20:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SPID_VERSION_MASK 0x001c0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SPID_VERSION_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: PID_VERSION [17:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PID_VERSION_MASK 0x00038000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PID_VERSION_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: BUF_OP_PIPE_SEL [14:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_BUF_OP_PIPE_SEL_MASK 0x00007000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_BUF_OP_PIPE_SEL_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: LAST_CHUNK [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_LAST_CHUNK_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_LAST_CHUNK_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: reserved0 [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_reserved0_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_reserved0_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SCRAM_INIT [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_INIT_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_INIT_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SCRAM_START [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_START_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_START_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: PKT_BUF_POINTER [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PKT_BUF_POINTER_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PKT_BUF_POINTER_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_10 - MCPB Channel x Stream Processor State Register 10 |
| ***************************************************************************/ |
| /* union - case NON_BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: reserved0 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_reserved0_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_reserved0_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR4 [15:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR4_MASK 0x0000f000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR4_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR3 [11:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR3_MASK 0x00000f00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR3_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR2 [07:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR2_MASK 0x000000f0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR2_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR1 [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR1_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR1_SHIFT 0 |
| |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: reserved0 [31:29] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_reserved0_MASK 0xe0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_reserved0_SHIFT 29 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: BLOCK_MODE_STATES [28:25] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_BLOCK_MODE_STATES_MASK 0x1e000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_BLOCK_MODE_STATES_SHIFT 25 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_VALID_5_WORDS [24:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_VALID_5_WORDS_MASK 0x01f00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_VALID_5_WORDS_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_5_VALID [19:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_5_VALID_MASK 0x000f0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_5_VALID_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_4_VALID [15:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_4_VALID_MASK 0x0000f000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_4_VALID_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_3_VALID [11:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_3_VALID_MASK 0x00000f00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_3_VALID_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_2_VALID [07:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_2_VALID_MASK 0x000000f0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_2_VALID_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_1_VALID [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_1_VALID_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_1_VALID_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_11 - MCPB Channel x Stream Processor State Register 11 |
| ***************************************************************************/ |
| /* union - case BLOCK_MODE [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: BLOCK_MODE :: EDR_W5 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W5_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W5_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: BLOCK_MODE :: EDR_W4 [15:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W4_MASK 0x0000ffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W4_SHIFT 0 |
| |
| /* union - case ASF [31:00] */ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: ASF :: ASF_PPI_PKT_LEN [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_ASF_ASF_PPI_PKT_LEN_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_ASF_ASF_PPI_PKT_LEN_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_12 - MCPB Channel x Stream Processor State Register 12 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_12 :: EDR_W3 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W3_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W3_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_12 :: EDR_W2 [15:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W2_MASK 0x0000ffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W2_SHIFT 0 |
| |
| /*************************************************************************** |
| *SP_STATE_REG_13 - MCPB Channel x Stream Processor State Register 13 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_13 :: EDR_W1 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_EDR_W1_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_EDR_W1_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_13 :: reserved0 [15:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_reserved0_MASK 0x0000ffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BBUFF_CTRL - MCPB Channel x Burst buffer control |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: reserved0 [31:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_reserved0_MASK 0xfffffc00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_reserved0_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: CRC_ERROR_PAUSE_EN [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_CRC_ERROR_PAUSE_EN_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_CRC_ERROR_PAUSE_EN_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: DMA_BBUFF_SLOT_WISE_READ_EN [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_DMA_BBUFF_SLOT_WISE_READ_EN_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_DMA_BBUFF_SLOT_WISE_READ_EN_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: STREAM_PROC_FEED_SIZE [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_STREAM_PROC_FEED_SIZE_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_STREAM_PROC_FEED_SIZE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BBUFF_CRC - MCPB Channel x Current CRC value |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CRC :: CRC_VALUE [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC_CRC_VALUE_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC_CRC_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BBUFF0_RW_STATUS - MCPB Channel x Burst buffer 0 data specific information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: reserved0 [31:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved0_MASK 0xf0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved0_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: FIRST_TRANS_AFTER_RUN [27:27] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_FIRST_TRANS_AFTER_RUN_MASK 0x08000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_FIRST_TRANS_AFTER_RUN_SHIFT 27 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: RESET_PARSER [26:26] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_RESET_PARSER_MASK 0x04000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_RESET_PARSER_SHIFT 26 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: DEPTH [25:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_DEPTH_MASK 0x03ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_DEPTH_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: reserved1 [15:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved1_MASK 0x0000f800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved1_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: BYTE_EN [10:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_BYTE_EN_MASK 0x00000780 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_BYTE_EN_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: CURR_READ [06:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_CURR_READ_MASK 0x0000007f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_CURR_READ_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BBUFF0_RO_STATUS - MCPB Channel x Burst buffer 0 control specific information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: reserved0 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_reserved0_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_reserved0_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PAUSE_AT_DESC_END [15:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_END_MASK 0x00008000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_END_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PAUSE_AT_DESC_RD [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_RD_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_RD_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: DESC_SLOT_NUM [13:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_DESC_SLOT_NUM_MASK 0x00002000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_DESC_SLOT_NUM_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: SECURE_RD [12:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_SECURE_RD_MASK 0x00001fe0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_SECURE_RD_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: ZERO_BYTE_TRAN [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_ZERO_BYTE_TRAN_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_ZERO_BYTE_TRAN_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: LAST_DATA_TRANS [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_LAST_DATA_TRANS_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_LAST_DATA_TRANS_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PUSH_RESIDUAL_BYTES [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PUSH_RESIDUAL_BYTES_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PUSH_RESIDUAL_BYTES_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: FORCE_TS_CONFIG [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_FORCE_TS_CONFIG_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_FORCE_TS_CONFIG_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: IS_ASF_PD_PACKET [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_IS_ASF_PD_PACKET_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_IS_ASF_PD_PACKET_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BBUFF1_RW_STATUS - MCPB Channel x Burst buffer 1 data specific information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: reserved0 [31:28] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved0_MASK 0xf0000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved0_SHIFT 28 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: FIRST_TRANS_AFTER_RUN [27:27] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_FIRST_TRANS_AFTER_RUN_MASK 0x08000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_FIRST_TRANS_AFTER_RUN_SHIFT 27 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: RESET_PARSER [26:26] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_RESET_PARSER_MASK 0x04000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_RESET_PARSER_SHIFT 26 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: DEPTH [25:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_DEPTH_MASK 0x03ff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_DEPTH_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: reserved1 [15:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved1_MASK 0x0000f800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved1_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: BYTE_EN [10:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_BYTE_EN_MASK 0x00000780 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_BYTE_EN_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: CURR_READ [06:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_CURR_READ_MASK 0x0000007f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_CURR_READ_SHIFT 0 |
| |
| /*************************************************************************** |
| *DMA_BBUFF1_RO_STATUS - MCPB Channel x Burst buffer 1 control specific information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: reserved0 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_reserved0_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_reserved0_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PAUSE_AT_DESC_END [15:15] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_END_MASK 0x00008000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_END_SHIFT 15 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PAUSE_AT_DESC_RD [14:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_RD_MASK 0x00004000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_RD_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: DESC_SLOT_NUM [13:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_DESC_SLOT_NUM_MASK 0x00002000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_DESC_SLOT_NUM_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: SECURE_RD [12:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_SECURE_RD_MASK 0x00001fe0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_SECURE_RD_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: ZERO_BYTE_TRAN [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_ZERO_BYTE_TRAN_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_ZERO_BYTE_TRAN_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: LAST_DATA_TRANS [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_LAST_DATA_TRANS_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_LAST_DATA_TRANS_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PUSH_RESIDUAL_BYTES [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PUSH_RESIDUAL_BYTES_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PUSH_RESIDUAL_BYTES_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: FORCE_TS_CONFIG [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_FORCE_TS_CONFIG_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_FORCE_TS_CONFIG_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: IS_ASF_PD_PACKET [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_IS_ASF_PD_PACKET_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_IS_ASF_PD_PACKET_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_BLOCKOUT_CTRL - MCPB Channel x Blockout control information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: reserved0 [31:31] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_reserved0_MASK 0x80000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_reserved0_SHIFT 31 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: BO_SPARE_BW_EN [30:30] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_SPARE_BW_EN_MASK 0x40000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_SPARE_BW_EN_SHIFT 30 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: BO_COUNT [29:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_COUNT_MASK 0x3fffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_NEXT_BO_MON - MCPB Channel x next Blockout monitor information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_NEXT_BO_MON :: NEXT_BO_MON [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON_NEXT_BO_MON_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON_NEXT_BO_MON_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_CTRL - MCPB Channel x next Blockout monitor information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved0 [31:25] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved0_MASK 0xfe000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved0_SHIFT 25 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_PAUSE_EN [24:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_PAUSE_EN_MASK 0x01000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_PAUSE_EN_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved1 [23:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved1_MASK 0x00c00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved1_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_RESTART [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_RESTART_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_RESTART_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_AUTOSTART_ON_ERROR_EN [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_ERROR_EN_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_ERROR_EN_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_AUTOSTART_ON_FORCE_RESYNC_EN [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_FORCE_RESYNC_EN_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_FORCE_RESYNC_EN_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_TYPE [18:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_TYPE_MASK 0x00060000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_TYPE_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_EN [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_EN_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_EN_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved2 [15:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved2_MASK 0x0000fe00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved2_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: GPC_SELECT [08:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_GPC_SELECT_MASK 0x000001f0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_GPC_SELECT_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: RE_TIMESTAMP_EN [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_RE_TIMESTAMP_EN_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_RE_TIMESTAMP_EN_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: OUTPUT_ATS_MODE [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_OUTPUT_ATS_MODE_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_OUTPUT_ATS_MODE_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: INPUT_ATS_FORMAT [01:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_INPUT_ATS_FORMAT_MASK 0x00000003 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_INPUT_ATS_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_REF_DIFF_VALUE_TS_MBOX - MCPB Channel x reference difference value and next Timestamp information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_TS_MBOX :: REF_DIFF_VALUE_TS_MBOX [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX_REF_DIFF_VALUE_TS_MBOX_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX_REF_DIFF_VALUE_TS_MBOX_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TS_ERR_BOUND_EARLY - MCPB Channel x TS error bound early information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_EARLY :: reserved0 [31:23] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_reserved0_MASK 0xff800000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_reserved0_SHIFT 23 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_EARLY :: TS_ERROR_BOUND [22:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_TS_ERROR_BOUND_MASK 0x007fffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_TS_ERROR_BOUND_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TS_ERR_BOUND_LATE - MCPB Channel x TS error bound late information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_LATE :: reserved0 [31:23] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_reserved0_MASK 0xff800000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_reserved0_SHIFT 23 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_LATE :: TS_ERROR_BOUND [22:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_TS_ERROR_BOUND_MASK 0x007fffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_TS_ERROR_BOUND_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_NEXT_GPC_MON - MCPB Channel x next Global Pacing Counter and Timestamp monitor information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_NEXT_GPC_MON :: NEXT_GPC_MON [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON_NEXT_GPC_MON_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON_NEXT_GPC_MON_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_REF_DIFF_VALUE_SIGN - MCPB Channel x reference difference value sign information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: reserved0 [31:14] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_reserved0_MASK 0xffffc000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_reserved0_SHIFT 14 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: LAST_NEXT_TS_VAL [13:13] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_NEXT_TS_VAL_MASK 0x00002000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_NEXT_TS_VAL_SHIFT 13 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: LAST_TS_DEL_VAL [12:12] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_TS_DEL_VAL_MASK 0x00001000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_TS_DEL_VAL_SHIFT 12 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MON_NEXT_TS [11:11] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_NEXT_TS_MASK 0x00000800 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_NEXT_TS_SHIFT 11 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MON_TS_DEL [10:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_TS_DEL_MASK 0x00000400 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_TS_DEL_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MBOX_NEXT_TS [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_NEXT_TS_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_NEXT_TS_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MBOX_TS_DEL [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_TS_DEL_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_TS_DEL_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MS2_BITS [07:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MS2_BITS_MASK 0x000000c0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MS2_BITS_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: PCR_TS_MS2_BITS [05:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_PCR_TS_MS2_BITS_MASK 0x00000030 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_PCR_TS_MS2_BITS_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: MSB_REF_DIFF_VALUE_SIGN [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_MSB_REF_DIFF_VALUE_SIGN_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_MSB_REF_DIFF_VALUE_SIGN_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_PES_PACING_CTRL - MCPB Channel x PES pacing control information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: reserved0 [31:25] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved0_MASK 0xfe000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved0_SHIFT 25 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN [24:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN_MASK 0x01000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: reserved1 [23:23] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved1_MASK 0x00800000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved1_SHIFT 23 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: NEXT_PACKET_TIMESTAMP_ERROR_BOUND [22:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_BOUND_MASK 0x007fffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_BOUND_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_SLOT_STATUS - MCPB Channel x Slot 0 and Slot 1 information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: reserved0 [31:26] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved0_SHIFT 26 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PARITY_ERROR_1 [25:25] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_1_MASK 0x02000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_1_SHIFT 25 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: MARKED_DISCON_IND_1 [24:24] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_1_MASK 0x01000000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_1_SHIFT 24 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PKT2PKT_TIMESTAMP_DELTA_VALID_1 [23:23] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_1_MASK 0x00800000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_1_SHIFT 23 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: NEXT_TIMESTAMP_VALID_1 [22:22] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_1_MASK 0x00400000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_1_SHIFT 22 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FORCE_RESYNC_1 [21:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_1_MASK 0x00200000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_1_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FIRST_PKT_AFTER_RUN_1 [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_1_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_1_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FORCE_RESYNC_1 [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_1_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_1_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FIRST_PKT_AFTER_RUN_1 [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_1_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_1_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_VALID_1 [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_1_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_1_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: TIMESTAMP_VALID_1 [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_1_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_1_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: reserved1 [15:10] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved1_MASK 0x0000fc00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved1_SHIFT 10 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PARITY_ERROR_0 [09:09] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_0_MASK 0x00000200 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_0_SHIFT 9 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: MARKED_DISCON_IND_0 [08:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_0_MASK 0x00000100 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PKT2PKT_TIMESTAMP_DELTA_VALID_0 [07:07] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_0_MASK 0x00000080 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_0_SHIFT 7 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: NEXT_TIMESTAMP_VALID_0 [06:06] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_0_MASK 0x00000040 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_0_SHIFT 6 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FORCE_RESYNC_0 [05:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_0_MASK 0x00000020 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_0_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FIRST_PKT_AFTER_RUN_0 [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_0_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_0_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FORCE_RESYNC_0 [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_0_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FIRST_PKT_AFTER_RUN_0 [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_0_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_0_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_VALID_0 [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_0_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_0_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: TIMESTAMP_VALID_0 [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_0_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_INFO_SLOT0_REG1 - MCPB Channel x timing information for Slot 0 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT0_REG1 :: TIMESTAMP_OR_NEXT_TS_0 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1_TIMESTAMP_OR_NEXT_TS_0_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1_TIMESTAMP_OR_NEXT_TS_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_INFO_SLOT0_REG2 - MCPB Channel x timing information for Slot 0 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT0_REG2 :: PCR_OR_TS_DELTA_0 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2_PCR_OR_TS_DELTA_0_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2_PCR_OR_TS_DELTA_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_INFO_SLOT1_REG1 - MCPB Channel x timing information for Slot 1 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT1_REG1 :: TIMESTAMP_OR_NEXT_TS_1 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1_TIMESTAMP_OR_NEXT_TS_1_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1_TIMESTAMP_OR_NEXT_TS_1_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_INFO_SLOT1_REG2 - MCPB Channel x timing information for Slot 1 |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT1_REG2 :: PCR_OR_TS_DELTA_1 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2_PCR_OR_TS_DELTA_1_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2_PCR_OR_TS_DELTA_1_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA - MCPB Channel x last TS delta value |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA :: LAST_TIMESTAMP_DELTA [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA_LAST_TIMESTAMP_DELTA_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA_LAST_TIMESTAMP_DELTA_SHIFT 0 |
| |
| /*************************************************************************** |
| *TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP - MCPB Channel x last NEXT TS value |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP :: LAST_NEXT_TIMESTAMP [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP_LAST_NEXT_TIMESTAMP_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP_LAST_NEXT_TIMESTAMP_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_STATUS - MCPB Channel x DCPM status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: reserved0 [31:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_reserved0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DESC_ADDRESS_STATUS [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_ADDRESS_STATUS_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_ADDRESS_STATUS_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DESC_DONE_INT_ADDRESS_STATUS [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_DONE_INT_ADDRESS_STATUS_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_DONE_INT_ADDRESS_STATUS_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DATA_ADDR_CUR_DESC_ADDR_STATUS [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DATA_ADDR_CUR_DESC_ADDR_STATUS_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DATA_ADDR_CUR_DESC_ADDR_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DESC_ADDR - MCPB Channel x DCPM descriptor address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR :: DESC_ADDRESS [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ADDRESS_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ADDRESS_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR :: DESC_ID [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ID_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ID_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DESC_DONE_INT_ADDR - MCPB Channel x DCPM descriptor done interrupt address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_DONE_INT_ADDR :: DESC_DONE_INT_ADDRESS [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ADDRESS_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ADDRESS_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_DONE_INT_ADDR :: DESC_DONE_INT_ID [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ID_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ID_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL - MCPB Channel x Pause after group of packets control information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: PAUSE_AFTER_PACKET_COUNT [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_PAUSE_AFTER_PACKET_COUNT_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_PAUSE_AFTER_PACKET_COUNT_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: BTP_PACKET_GROUP_ID [15:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_BTP_PACKET_GROUP_ID_MASK 0x0000ff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_BTP_PACKET_GROUP_ID_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: reserved0 [07:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_reserved0_MASK 0x000000f8 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_reserved0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: DIS_DUPLICATION_COUNTING [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DIS_DUPLICATION_COUNTING_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DIS_DUPLICATION_COUNTING_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: DONT_SEND_BTP_PACKET [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DONT_SEND_BTP_PACKET_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DONT_SEND_BTP_PACKET_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: ENABLE [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_ENABLE_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_ENABLE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER - MCPB Channel x Pause after group of packets local packet counter |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER :: reserved0 [31:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_reserved0_MASK 0xffff0000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_reserved0_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER :: PKT_COUNTER [15:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_PKT_COUNTER_MASK 0x0000ffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_PKT_COUNTER_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_LOCAL_PACKET_COUNTER - MCPB Channel x local packet counter |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_LOCAL_PACKET_COUNTER :: PACKET_COUNTER [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER_PACKET_COUNTER_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER_PACKET_COUNTER_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DATA_ADDR_UPPER - MCPB Channel x DCPM data address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_UPPER :: DATA_ADDR [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_DATA_ADDR_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_DATA_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DATA_ADDR_LOWER - MCPB Channel x DCPM data address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_LOWER :: DATA_ADDR [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER_DATA_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER_DATA_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_CURR_DESC_ADDR - MCPB Channel x DCPM current descriptor address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_SLOT_STATUS - MCPB Channel x DCPM slot status information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: reserved0 [31:21] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved0_MASK 0xffe00000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved0_SHIFT 21 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_READ_INTR_1 [20:20] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_1_MASK 0x00100000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_1_SHIFT 20 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_END_INTR_1 [19:19] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_1_MASK 0x00080000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_1_SHIFT 19 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_UPDATE_1 [18:18] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_1_MASK 0x00040000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_1_SHIFT 18 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_DONE_INT_UPDATE_1 [17:17] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_1_MASK 0x00020000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_1_SHIFT 17 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DATA_ADDR_CUR_DESC_ADDR_UPDATE_1 [16:16] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_1_MASK 0x00010000 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_1_SHIFT 16 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: reserved1 [15:05] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved1_MASK 0x0000ffe0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved1_SHIFT 5 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_READ_INTR_0 [04:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_0_MASK 0x00000010 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_0_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_END_INTR_0 [03:03] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_0_MASK 0x00000008 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_0_SHIFT 3 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_UPDATE_0 [02:02] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_0_MASK 0x00000004 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_0_SHIFT 2 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_DONE_INT_UPDATE_0 [01:01] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_0_MASK 0x00000002 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_0_SHIFT 1 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DATA_ADDR_CUR_DESC_ADDR_UPDATE_0 [00:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_0_MASK 0x00000001 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DESC_ADDR_SLOT_0 - MCPB Channel x DCPM completed slot 0 descriptor address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_0 :: DESC_ADDR_SLOT_0 [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ADDR_SLOT_0_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ADDR_SLOT_0_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_0 :: DESC_ID_SLOT_0 [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ID_SLOT_0_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ID_SLOT_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DATA_ADDR_SLOT_0_UPPER - MCPB Channel x DCPM completed slot 0 data address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_UPPER :: DATA_ADDR_0 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_DATA_ADDR_0_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_DATA_ADDR_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DATA_ADDR_SLOT_0_LOWER - MCPB Channel x DCPM completed slot 0 data address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_LOWER :: DATA_ADDR_0 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER_DATA_ADDR_0_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER_DATA_ADDR_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DESC_ADDR_SLOT_1 - MCPB Channel x DCPM completed slot 1 descriptor address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_1 :: DESC_ADDR_SLOT_1 [31:04] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ADDR_SLOT_1_MASK 0xfffffff0 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ADDR_SLOT_1_SHIFT 4 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_1 :: DESC_ID_SLOT_1 [03:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ID_SLOT_1_MASK 0x0000000f |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ID_SLOT_1_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DATA_ADDR_SLOT_1_UPPER - MCPB Channel x DCPM completed slot 1 data address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_UPPER :: reserved0 [31:08] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_reserved0_MASK 0xffffff00 |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_reserved0_SHIFT 8 |
| |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_UPPER :: DATA_ADDR_1 [07:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_DATA_ADDR_1_MASK 0x000000ff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_DATA_ADDR_1_SHIFT 0 |
| |
| /*************************************************************************** |
| *DCPM_DATA_ADDR_SLOT_1_LOWER - MCPB Channel x DCPM completed slot 1 data address information |
| ***************************************************************************/ |
| /* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_LOWER :: DATA_ADDR_1 [31:00] */ |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER_DATA_ADDR_1_MASK 0xffffffff |
| #define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER_DATA_ADDR_1_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_XPT_MEMDMA_MCPB_CH0_H__ */ |
| |
| /* End of File */ |
